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Fix memory operand order in Verilator traces #3572

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Fix memory operand order in Verilator traces #3572

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32 changes: 32 additions & 0 deletions verif/sim/test_verilator_log_to_trace_csv.py
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Original file line number Diff line number Diff line change
@@ -0,0 +1,32 @@
# Copyright 2026 Hyeonuk Jeong
# SPDX-License-Identifier: Apache-2.0

import csv
import sys
from pathlib import Path

import pytest

sys.path.insert(0, str(Path(__file__).parent / "dv/scripts"))
from verilator_log_to_trace_csv import process_verilator_sim_log


@pytest.mark.parametrize("disasm,operand", [
("lw t0, 4(sp)", "t0,sp,4"),
("sw t0, -4(sp)", "t0,sp,-4"),
("ld a0, 16(s0)", "a0,s0,16"),
("sd a0, 0(s0)", "a0,s0,0"),
("flw fa0, 8(sp)", "fa0,sp,8"),
("fsd fa0, -8(sp)", "fa0,sp,-8"),
("addi t0, sp, 4", "t0,sp,4"),
])
def test_memory_operand_order(tmp_path, disasm, operand):
logfile = tmp_path / "trace.log"
logfile.write_text(
f"core 0: 0x0000000080000000 (0x00412283) {disasm}\n")
output = tmp_path / "trace.csv"
assert process_verilator_sim_log(str(logfile), str(output), full_trace=1) == 1
with output.open() as handle:
entries = list(csv.DictReader(handle))
assert entries[0]["operand"] == operand
assert entries[0]["pc"] == "0000000080000000"
10 changes: 8 additions & 2 deletions verif/sim/verilator_log_to_trace_csv.py
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Original file line number Diff line number Diff line change
Expand Up @@ -32,6 +32,7 @@
"\((?P<bin>.*?)\) (?P<reg>[xf]\s*\d*?) 0x(?P<val>[a-f0-9]+)")
CORE_RE = re.compile(r"core.*0x(?P<addr>[a-f0-9]+?) \(0x(?P<bin>.*?)\) (?P<instr>.*?)$")
ILLE_RE = re.compile(r"trap_illegal_instruction")
ADDR_RE = re.compile(r"(?P<rd>[a-z0-9]+),(?P<imm>-?[0-9]+)\((?P<rs1>[a-z0-9]+)\)")

LOGGER = logging.getLogger()

Expand All @@ -46,8 +47,13 @@ def process_instr(trace):
else:
imm = str(int(imm, 16))
trace.operand = trace.operand[0:idx+1] + imm
trace.operand = trace.operand.replace("(", ",")
trace.operand = trace.operand.replace(")", "")
address = ADDR_RE.fullmatch(trace.operand)
if address:
trace.operand = "{},{},{}".format(address.group("rd"),
address.group("rs1"),
address.group("imm"))
else:
trace.operand = trace.operand.replace("(", ",").replace(")", "")


def read_verilator_instr(match, full_trace):
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