Fix memory operand order in Verilator traces - #3572
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maikjjeong wants to merge 1 commit into
Open
maikjjeong wants to merge 1 commit into
maikjjeong wants to merge 1 commit into
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The Verilator trace converter turns a memory operand such as
lw t0,4(sp)intot0,4,sp. The standard trace format used by the Spike converter and instruction coverage ist0,sp,4, so the base register and displacement are reversed.Recognize register/displacement(base) operands explicitly and emit register/base/displacement order. Preserve the existing handling of other operands.
Validation: seven pytest cases exercise the real log-to-CSV path with integer and floating-point loads/stores, positive/negative/zero offsets, and a non-memory instruction. Six fail on the parent revision; all seven pass after the fix. The tests use the repository's pinned riscv-dv submodule. No RTL changes are included.
Prepared with Codex assistance. The human contributor has reviewed and understood the change and endorsed its submission.