[EG, AST] Move AST inside the top - #31442

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etterli wants to merge 24 commits into

lowRISC:masterfrom

etterli:eg-ast-move

Commits on Sep 28, 2026

[ast,rtl] Rename partitions to match topgen convention
etterli
committed
877acd0
[ast,rtl] Prepare power status signals for split AST integration
etterli
committed
3967779
[ast,rtl] Remove ifdef from port lists
etterli
committed
d500b97
[ast,rtl] Use awire_t for analog outputs
etterli
committed
ef037c8
[ast,rtl] Parameterize width of ast port signals
etterli
committed
7d8f9b5
[ast,rtl] Make power on reset comportable
etterli
committed
6afee29
[ast,rtl] Make alert signals inter-module signal comportable
etterli
committed
645c602
[ast,rtl] Fix typo in power status
etterli
committed
c140766
[ast,rtl] Add dedicated PowerOnReset signal port for rstmgr
etterli
committed
8c78fa1
[ast,rtl] Refactor ADC interface to structs
etterli
committed
47489f7
[ast,rtl] Make scan reset comportable
etterli
committed
242fd6c
[ast,rtl] Rename ast_init_done to init_done
etterli
committed
dc9c5d3
[ast,rtl] Rename entropy ports to edn
etterli
committed
dcdb9e3
[ast,rtl] Combine vx_supp signals into a struct for comportability
etterli
committed
7d4e85e
[ast,rtl] Combine observation signals into a struct for comportability
etterli
committed
5066f74
[ast,rtl] Make main power domain reset comportable
etterli
committed
671523d
[ast,rtl] Split mem_cfg per partition and move generation inside secondary partition
etterli
committed
908ba1a
[ast,rtl] Use pwrmgr struct for all signals interfacing with pwrmgr
etterli
committed
93b9345
[ast,rtl] Add port for IO power state
etterli
committed
aea1e66
[topgen] Add template for memory configuration wiring
etterli
committed
0da525c
[ast,hjson] Declare AST as a split IP
etterli
committed
8be31e4
[top_earlgrey] Move AST inside top
etterli
committed
e29a7b4
[top_earlgrey,dv] Adapt DV to internal AST module
etterli
committed
797c228
[top_earlgrey] Autogenerated files for AST split
etterli
committed
c1d3f88

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[EG, AST] Move AST inside the top - #31442

[EG, AST] Move AST inside the top#31442
etterli wants to merge 24 commits into
lowRISC:masterfrom
etterli:eg-ast-move

Commits on Sep 28, 2026

[ast,rtl] Rename partitions to match topgen convention

[ast,rtl] Prepare power status signals for split AST integration

[ast,rtl] Remove ifdef from port lists

[ast,rtl] Use awire_t for analog outputs

[ast,rtl] Parameterize width of ast port signals

[ast,rtl] Make power on reset comportable

[ast,rtl] Make alert signals inter-module signal comportable

[ast,rtl] Fix typo in power status

[ast,rtl] Add dedicated PowerOnReset signal port for rstmgr

[ast,rtl] Refactor ADC interface to structs

[ast,rtl] Make scan reset comportable

[ast,rtl] Rename ast_init_done to init_done

[ast,rtl] Rename entropy ports to edn

[ast,rtl] Combine vx_supp signals into a struct for comportability

[ast,rtl] Combine observation signals into a struct for comportability

[ast,rtl] Make main power domain reset comportable

[ast,rtl] Split mem_cfg per partition and move generation inside secondary partition

[ast,rtl] Use pwrmgr struct for all signals interfacing with pwrmgr

[ast,rtl] Add port for IO power state

[topgen] Add template for memory configuration wiring

[ast,hjson] Declare AST as a split IP

[top_earlgrey] Move AST inside top

[top_earlgrey,dv] Adapt DV to internal AST module

[top_earlgrey] Autogenerated files for AST split