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[EG, AST] Move AST inside the top - #31442

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[EG, AST] Move AST inside the top#31442
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@etterli etterli commented Sep 23, 2026 •
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This is a draft and requires #31220 and #31326 to be merged first.

For now it serves as review context for #31326.
Only the last 5 commits are of relevance.

This moves the Earlgrey's AST from the chip level inside the power domains. AST is now instantiated properly as split IP.

@etterli etterli mentioned this pull request Sep 23, 2026
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etterli and others added 25 commits September 24, 2026 14:16
@etterli
[ast,rtl] Rename partitions to match topgen convetion
922d3c3 
This is a preparation to make AST a topgen conform split IP.

This renames the aon_main to ast_part_primary and ast_aon to ast_part_secondary.
Similary, it also renames the intra-IP connections to p2s and s2p. Note that the actual aon/main names
for clocks and resets are kept. These are independent of the partitioning.

Signed-off-by: Pascal Etterli <pascal.etterli@lowrisc.org>
@etterli
[ast,rtl] Prepare power status signals for split AST integration
0fd4071 
This adds local signals for ast_pwst_o and ast_pwst_h_o such that DV can target these local nets.
This is a preparation for when AST will be instantiated as split IP inside Earlgrey and some of the
signals from these structs will be forwarded to modules via other signals. When DV targets these
local nets, all consumers of the power status information receive the change.

Signed-off-by: Pascal Etterli <pascal.etterli@lowrisc.org>
@etterli
[ast,rtl] Remove ifdef from port lists
6e689a7 
This makes the AST partitions' port list non-conditional by always exposing the clock bypass input.
This input is only required for FPGA / Verilator designs. reggen/topgen however do not support
conditional port lists.

Signed-off-by: Pascal Etterli <pascal.etterli@lowrisc.org>
@etterli
[ast,rtl] Use awire_t for analog outputs
05163a9 
This replaces the hardcoded output type of the analog output signals with a type which
properly resolves the signal type at compile-time.

It also renames the analog IOs from  x_ai to x_a_i as topgen does only support _i suffixes (same for
_o).

Signed-off-by: Pascal Etterli <pascal.etterli@lowrisc.org>
@etterli
[ast,rtl] Parameterize width of ast port signals
eaca189 
This uses parameters for array interface signals so that the partitions no longer directly depend on
the ast_pkg.sv values. This is a preparation when these signals are converted to inter-module wired
by topgen.

Signed-off-by: Pascal Etterli <pascal.etterli@lowrisc.org>
@etterli
[ast,rtl] Make power on reset comportable
17a8ccf 
This renames the por_ni pin to por_n_i such that it complies with topgen's naming convention. This
reset is not handled as a proper reset in the tooling so _ni is not a valid suffix.

Signed-off-by: Pascal Etterli <pascal.etterli@lowrisc.org>
@etterli
[ast,rtl] Make alert signals inter-module signal comportable
92389a4 
This renames the alert signals such that the names are valid names for inter-module signals

Signed-off-by: Pascal Etterli <pascal.etterli@lowrisc.org>
@etterli
[ast,rtl] Fix typo in power status
cebd09c 
Signed-off-by: Pascal Etterli <pascal.etterli@lowrisc.org>
@etterli
[ast,rtl] Add dedicated PowerOnReset signal port for rstmgr
20ef63b 
This adds a port exposing the PowerOnResets for the main and aon partition such that it can be
directly connected to the rstmgr. This will simplify the AST move inside the partitions.

Signed-off-by: Pascal Etterli <pascal.etterli@lowrisc.org>
@etterli
[ast,rtl] Refactor ADC interace to structs
892ad3d 
This combines the separate signals of the ADC interface into the already existing ADC req/rsp
structs. This simplifies the move of AST inside the partitions.

Signed-off-by: Pascal Etterli <pascal.etterli@lowrisc.org>
@etterli
[ast,rtl] Make scan reset comportable
73b5739 
This renames scan_rst_no to *_n_o such that it can be defined as inter-module signal. Topgen does
not support _no suffixes except for explictly declared resets.

Signed-off-by: Pascal Etterli <pascal.etterli@lowrisc.org>
@etterli
[ast,rtl] Rename ast_inti_done to init_done
e8d2ee4 
This makes the name more consise as well as prevents a double 'ast' prefix once this signal is
connected via an inter-module connection (it would be named ast_ast_init_done).

Signed-off-by: Pascal Etterli <pascal.etterli@lowrisc.org>
@etterli
[ast,rtl] Rename entropy ports to edn
d1ac357 
This alignes the EDN ports to the common naming scheme used in Earlgrey

Signed-off-by: Pascal Etterli <pascal.etterli@lowrisc.org>
@etterli
[ast,rtl] Combine vx_supp signals into a struct for comportability
6c7e711 
This combines the 5 supply test pins into a struct. A struct can easier be used for an inter-module
connection. This simplifies the move of AST into the partitions.

Signed-off-by: Pascal Etterli <pascal.etterli@lowrisc.org>
@etterli
[ast,rtl] Combine observation signals into a struct for comportability
d49f72a 
This combines the 4 bus observations signals into a struct. A struct can easier be used for an inter-module
connection. This simplifies the move of AST into the partitions.

Signed-off-by: Pascal Etterli <pascal.etterli@lowrisc.org>
@etterli
[ast,rtl] Make main power domain reset comportable
c4096d7 
This renames main_pd_ni to main_pd_n_i such that it can be defined as inter-module signal. Topgen
does not support _no suffixes except for explictly declared resets.

Signed-off-by: Pascal Etterli <pascal.etterli@lowrisc.org>
@etterli
[ast,rtl] Split mem_cfg per partition and move generation inside seco…
f93125e 
…ndary partition

This moves the memory configuration req/rsp generation inside the secondary partition (note these
are dummies for open-source code). It also splits the requests into primary and secondary structs
such that each partition can forward the req/rsp to the consumers locally. This requires to forward
mem_cfgs for the primary partition via the intra-IP connection.

This whole change is motivated to simplify moving the AST inside the power domains.

Signed-off-by: Pascal Etterli <pascal.etterli@lowrisc.org>
@etterli
[ast,rtl] Use pwrmgr struct for all signals interfacing with pwrmgr
9771cf7 
Previously, the signals from/to AST to/from pwrmgr were separate signals of the AST interface. This
consolidates this to a single pwrmgr struct interface and forwards/receives the AST-primary signals
via the intra-IP connection.

Signed-off-by: Pascal Etterli <pascal.etterli@lowrisc.org>
@etterli
[ast,rtl] Add port for IO power state
6b9f301 
This adds a port for the signals about the current power state going to the sensor_ctrl. These were
routed via the chip if the AST was on chip level. We now add a struct to enable topgen inter-module
connections.

Signed-off-by: Pascal Etterli <pascal.etterli@lowrisc.org>
@etterli
[reggen] Validate clocking and pwrmgr connections for split IPs
d403bc7 
A wakeup or reset-request is wired to pwrmgr through an inter-module signal of the same name. For a
split IP this reference is resolved per partition, so reggen now requires the wakeup or
reset-request to be declared in the same partition as its inter-module signal. This rejects a
mismatch early instead of letting it surface as an unresolved inter-module reference in topgen.

Also require a split IP to always declare clockings for its secondary partition.

Signed-off-by: Pascal Etterli <pascal.etterli@lowrisc.org>
@etterli
[reggen] Document that split IPs can use req_rsp signals for intra-IP…
48a241d 
… connections

This was not possible with the planned topgen changes. But the new implementation will allow this.

Signed-off-by: Pascal Etterli <pascal.etterli@lowrisc.org>
@etterli
[topgen] Properly resolve inter-module widths
37df7cd 
The inter-module array-width check compared req/rsp widths that may be Parameter objects rather than
plain ints. This factors the width resolution into a helper and resolves the requester width as
well, such that the req/rsp array comparison always operates on integers.

Signed-off-by: Pascal Etterli <pascal.etterli@lowrisc.org>
@etterli @glaserf
[topgen] Handle intra-IP and inter-module signals for split IPs
8cc8f9a 
A split IP can have intra-IP connections which directly connect the two partitions. However, in the
config a split IP is a single instance. So any regular inter-module signal would have the same start
and end point, which is not supported by the current topgen.

This commit thus introduces an intra-IP signal handling which uniquifies inter-module signals per
partition. It does so by adding a partition qualifier to each inter-module signal of a split IP.
This allows the regular inter-module signal handling to connect the two partitions properly.

It also enables the partitions to use the same signal name, otherwise these would have to be unique.

Non-split IPs use no qualifier.

Co-authored-by: Florian Glaser <glaserf@lowrisc.org>
Signed-off-by: Pascal Etterli <pascal.etterli@lowrisc.org>
@etterli
[topgen] Qualify autogenerated pwrmga/clkmgr connections per partition
af286c3 
Wakeup, reset-request and idle-hint connections to pwrmgr/clkmgr were currently generated as
<module>.<signal> references. For a split IP, Inter-module names are only unique per partition. This
would give an ambigious signal choice. This commit adds logic to qualify these references with the
signal's partition. Non-split IPs stay unqualified.

Signed-off-by: Pascal Etterli <pascal.etterli@lowrisc.org>
@etterli @glaserf
[topgen] Extend validation for split IPs
2ecc524 
Extends the hjson validator to handle the additional keys for split IPs.

This prepares topgen to handle split IPs. topgen will emit additional keys for partitioned / split
IPs. This commits adds the required code to validate such a configuration. It checks the secondary
keys as well as that the split is configured properly.

Co-authored-by: Florian Glaser <glaserf@lowrisc.org>
Signed-off-by: Pascal Etterli <pascal.etterli@lowrisc.org>
@etterli
etterli force-pushed the eg-ast-move branch 4 times, most recently from 54cc062 to 062b269 Compare September 24, 2026 21:12
etterli and others added 14 commits September 25, 2026 13:55
@etterli @glaserf
[topgen] Support elaborating split IPs
399985e 
A split IP has nested dictionaries for certain keys. This flattens such a configuration by emitting
keys for the secondary partition. It also adapts all the elaboration logic such that it can handle
multiple partitions. It also validates that any secondary partition has proper clocking information.

Co-authored-by: Florian Glaser <glaserf@lowrisc.org>
Signed-off-by: Pascal Etterli <pascal.etterli@lowrisc.org>
@etterli
[topgen] Validate power domains before using this information
fc1d185 
topgen uses certain power domain names before the actual validation code is run. This can lead to
unexpected crashes especially when handling split IPs.

This commit moves the domain validation before any of the domain information is used. This is
possible as it is completely top dependend and does not require knowledge about the actual IPs.

A consequence of this is that the domain key is emitted earlier as before in the autogen hjson
files. Otherwise there is no functional change.

Signed-off-by: Pascal Etterli <pascal.etterli@lowrisc.org>
@etterli @glaserf
[topgen] Support split IPs
cd0293a 
This commit finally adds the full support for split IPs.

A split IP consists of two partitions which can be instantiated in different power domains. topgen
then automatically resolves the inter-module connections as well as intra-IP connections.

All registers (TL-UL) stay in the primary partition. So do RACL and scan/DFT ports.

Co-authored-by: Florian Glaser <glaserf@lowrisc.org>
Signed-off-by: Pascal Etterli <pascal.etterli@lowrisc.org>
@etterli
[topgen] Document the split IP support
b984e9c 
Adds some basic documentation how to integrate a split IP into a top.

Signed-off-by: Pascal Etterli <pascal.etterli@lowrisc.org>
@etterli
[topgen] Support external clocks on top level
c571583 
This extends the templates such that external clocks are properly wired down to the receiving power
domains.

Signed-off-by: Pascal Etterli <pascal.etterli@lowrisc.org>
@etterli
[topgen] Support clock sources inside the top
e974b4e 
This extends topgen such that clocks can be sourced inside a partition/domain. Previously, clocks
would have to be provided from outside a top. This now allows a clock to be inside a partition which
then can be distributed to all domains/partitons.

It has also implications on DFT signals. These are originating inside the top instead of being
provided externally.

Signed-off-by: Pascal Etterli <pascal.etterli@lowrisc.org>
@etterli
[topgen] Alerts may not be driven by raw clocks
41885b9 
If a clock driving an alert was assigned to an 'ext' clock group,
topgen generated an alert clock gate connection to a clock gate signal
which did not exist as the clkmgr does not gate such a clock.

This adds the required check for this and raises an error.

Signed-off-by: Pascal Etterli <pascal.etterli@lowrisc.org>
@etterli
[topgen] Make xbar connections clock aware
aeca291 
Previously, the xbar drivers assumed that each IP drives it xbar logic with clk_i. This commit
generalized this such that the IP's primary clock is used.

This is required for the AST split.

Signed-off-by: Pascal Etterli <pascal.etterli@lowrisc.org>
@etterli
[topgen] Document internally generated clocks
56c21c1 
This adds a small explanation how to define a clock which is generated
inside the top and is not provided from external.

Signed-off-by: Pascal Etterli <pascal.etterli@lowrisc.org>
@etterli
[topgen] Add template for memory configuration wiring
8384423 
This adds a small template which connects memory configurations from a unified struct to signals
connecting to the consumers. It can be used inside a power domain to generate the local memory
configuration wiring required to connect to the AST partitions.

Signed-off-by: Pascal Etterli <pascal.etterli@lowrisc.org>
@etterli
[ast,hjson] Declare AST as a split IP
bc5560b 
Adaptes the hjson of AST such that it represents a split IP which can be instantiated inside a top.

Signed-off-by: Pascal Etterli <pascal.etterli@lowrisc.org>
@etterli
[top_earlgrey] Move AST inside top
bce9736 
This moves the AST from the chip level inside the top. AST is instantiated as a split IP with
partitions in the AON and main power domain. This requires a substantial rewiring of clocks, resets,
and other AST related signals. It also touches DFT signals as, e.g., EG's scan_mode source is now
inside the top and no longer generated at chip level.

Signed-off-by: Pascal Etterli <pascal.etterli@lowrisc.org>
@etterli
[top_earlgrey,dv] Adapt DV to internal AST module
44f0b80 
This makes the required changes to DV after the AST module was moved into the top and split into two
partitions.

Signed-off-by: Pascal Etterli <pascal.etterli@lowrisc.org>
@etterli
[top_earlgrey] Autogenerated files for AST split
0aa0ab2 
This contains all the autogenerated updates due to the AST split / move
into the top.

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