Conditioned 3.5kHz Oscillator Design

Project Overview

This project focuses on the design, simulation, and implementation of a highly precise and robust 3.5 kHz analog signal generation system. Utilizing a Wein Bridge oscillator paired with Active Filtering and a strategic amplification stage, the design is specifically hardened against high, low frequency noise factors to deliver a stable $7\mathrm{V_{pk}}$ with 4% tolerance.

The circuit was tested with High, Low and thermal noise present at different temperatures in SPICE (MultiSim) to verify compliance with the 4% tolerance. The circuit was also assembled physically with a breadboard, and worked as expected.

Front 3D Render	Bottom 3D Render

Technical Specifications & Features

1. Low-Distortion Tone Generation

• Wein-Bridge Oscillator Architecture: The source stage centers around an active Wein-Bridge topology oscillating at $3.51\text{ kHz}$ utilizing precision matching components ($R = 4.53\text{ k}\Omega, C = 10\text{ nF}$).
• Amplitude Stabilization Network: Employs a fast-acting parallel diode ($1\text{N}4148$) and scaling resistor feedback matrix ($22.5\text{ k}\Omega$ and $121\text{ k}\Omega$). This dynamic automatic gain configuration scales the peak voltage to exactly $1.91\text{ V}_{\text{rms}}$ at the oscillator output (Vo1 or WBOutput), introducing immunity against system-level noise paths.

2. High-Order Active Filtering

To isolate the fundamental tone from harmonic components and ambient thermal or high/low-frequency noise, the signal passes through a cascaded 4th-order active bandpass network:

• Order-2 Sallen-Key Low Pass Filter (LPF): Configured with a distinct cutoff frequency ($f_c$) of $3.6\text{ kHz}$ ($R = 4.42\text{ k}\Omega, C = 10\text{ nF}$).
• Order-2 Sallen-Key High Pass Filter (HPF): Cascaded immediately after the LPF with a cutoff frequency ($f_c$) of $3.43\text{ kHz}$ ($R = 4.64\text{ k}\Omega, C = 10\text{ nF}$).

3. Precision Output Amplification

• Non-Inverting Gain Stage: The final block uses a non-inverting operational amplifier configuration where $R_i = R_f = 10\text{ k}\Omega$, introducing a precise gain multiplier of $A_v = 2$.
• Impedance Matching & Compensation: Implements a $4.99\text{ k}\Omega$ bias compensation resistor ($R_c$) at the non-inverting node to mitigate DC offset vulnerabilities caused by input bias currents.
• Voltage Targets: The stage scales the input signal up to a theoretical $7\mathrm{V_{pk}}$ ($4.95\mathrm{V_{rms}}$) target.

---

Hardware Validation & Performance Results

SPICE Simulation vs. Laboratory Measurements

The complete system architecture was thoroughly simulated using SPICE models (Multisim) under active temperature ($45^\circ\text{C}$) and wideband noise environments ($1\text{ MHz}$ thermal bandwidth) before physical assembly:

Parameter	Design Requirement	SPICE Simulation	Physical Lab Measurement	Status
Oscillation Frequency	$3.50\text{ kHz}$	$3.49\text{ kHz} - 3.50\text{ kHz}$	Verified via Scope	Passed
Pre-Filtered Amplitude	N/A	$1.91\text{ V}_{\text{rms}}$	Verified via Scope	Passed
Final System Output	$7\mathrm{V_{pk}}$ ($4.95\mathrm{V_{rms}}$) $\pm~4$%	$4.98\mathrm{V_{rms}} - 4.99\mathrm{V_{rms}}$	$4.86\mathrm{V_{rms}}$ ($6.87\mathrm{V_{pk}}$)	Passed (< 2.8% Error)

Active circuit stages are realized through low-noise LF353N dual JFET-input operational amplifiers, ensuring clean signal paths, fast slew rates, and minimal distortion from source to output.

---

Physical Implementation

To confirm hardware viability, the system was prototyped and benchmarked using laboratory instrumentation. The physical implementation successfully kept the final output voltage well within the strict $\pm 4$% design window, yielding an experimental value of $4.86\text{ V}_{\text{rms}}$ ($2.8%$ absolute error from target).

Prototype Gallery

1. Hardware Prototype: Physical layout showcasing the cascaded LF353N op-amp stages and the precision component matching network.
2. Oscilloscope Waveform: Real-time capture of the Wien bridge oscillator output node confirming core stability, target frequency generation, and diode network clamping behaviors.
3. DMM Output Verification: Digital Multimeter reading establishing a final system output of $4.86\text{ V}_{\text{rms}}$, verifying mathematical and simulation model integrity on hardware.