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- add architecture-independent msixbackend abstractioin - implement MSI-X backend for GICv3 - refactor vpci_dev to remove arch-specific dependencies - refine virtio-pci device access interface
Merge guest IPI action bits, publish blocking sends before return, and keep the virtual IPI line asserted until all pending actions are cleared.
Maintain asserted HWI bits per physical CPU, update only GINTC.VIP, preserve PIP and HC, and remove timer-driven global injection cleanup.
Pass the target zone and IRQ through HvClearInjectIrq so backends can deassert one guest interrupt line without clearing unrelated pending interrupts.
fix(loongarch64): make SMP IPI and Virtio IRQ delivery stateful
align LS3A5000 VirtIO IRQ and make HWI lock per-CPU
ci(x86_64): add Asterinas zone1 Jenkins test
Add overlap check between MMIO passthrough regions and MMIO intercept handler regions
* fix(loongarch64): preserve firmware PCI bridge bus numbers * fix(pci): preserve firmware bridge bus topology Cache the firmware-programmed bridge bus register during enumeration for no_pcie_bar_realloc backends. Preserve it for identity bus mappings and translate primary, secondary, and subordinate bus numbers when a zone remaps buses. * fix(pci): initialize bridge state before bus mapping Cache PCI configuration values before set_vbdf initializes the virtual bridge bus register. Also require at least one visible bus mapping before treating a bridge topology as identity-mapped.
chore(release): prepare v0.6 release
li041
approved these changes
Aug 25, 2026
liulog
approved these changes
Aug 25, 2026
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This PR merges
devintomainto cut thev0.6release.