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1. 3x3-systolic-array-multiplier 3x3-systolic-array-multiplier Public

   This verilog code implements a fully synthesiable 3x3 systolic array multiplier. There are already built in buffers so that there is no need for delaying the inputs into this design.

   Verilog

2. The-OpenROAD-Project/OpenROAD The-OpenROAD-Project/OpenROAD Public

   OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

   Verilog 3.1k 1k