arm64: dts: qcom: nord: Enable I2C18 and SPI16 - #1747
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Aniket Randive (AniketRandive-coder) wants to merge 831 commits into
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arm64: dts: qcom: nord: Enable I2C18 and SPI16#1747Aniket Randive (AniketRandive-coder) wants to merge 831 commits into
Aniket Randive (AniketRandive-coder) wants to merge 831 commits into
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Nord provides two USB3+DP combo PHYs. This is the v6 block so add the new offsets table. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> [ shawn: Drop qmp_v4_calibrate_dp_phy to fix compile error seen on next-20260814 due to commit 8fd2b30 ("phy: qcom: qmp-combo: Drop qmp_v4_calibrate_dp_phy") ] Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Add a compatible for the eUSB2 PHY found on the Qualcomm Nord (SA8797P) SoC. It is compatible with the sm8550 eUSB2 PHY. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
Not every instance of this PHY has a block reset of its own. On Nord (SA8797P) there are three eUSB2 PHYs but only two QUSB2PHY block resets: the HS-only USB20 tile has no dedicated PHY reset and is instead reset as a whole through the controller's own USB20_PRIM_BCR. Requiring 'resets' makes that instance impossible to describe, since the controller and the PHY cannot both claim the single block reset exclusively. The driver has always treated the reset as optional - it uses devm_reset_control_get_optional_exclusive() - and the sibling samsung,exynos2200-eusb2-phy binding, which is served by the same driver, does not require it either. Drop it from the required list. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
Add a compatible for the DWC3 USB controller found on the Qualcomm Nord (SA8797P) SoC. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
The clock-domain synchronizers inside the Nord USB tiles require their clocks to be running for a block reset release to propagate. With the current ordering the reset is deasserted while the clocks are still disabled and the controller register interface comes up unresponsive. Enable the clocks first. This is harmless on platforms that already work, since the reset is cycled anyway. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
On some Qualcomm eUSB2 designs the DWC3 core register interface is clocked by the HS PHY's UTMI clock. The PHY must be initialized before the very first core register access, otherwise that access faults with a synchronous external abort. Add an early_phy_init flag to struct dwc3_probe_data and a dwc3_core_early_phy_init() helper that gets and initializes the HS generic PHY, then invokes a new post_phy_init() glue op so the glue can complete any PHY-clock-dependent controller setup before the first core register access. There's no functional change for existing platforms for now. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
On Nord's HS-only USB20 tile the QSCRATCH register interface is clocked by the eUSB2 PHY's UTMI clock. Writing the select-utmi-as-pipe-clk configuration from probe() happens before the PHY is initialized and faults with a synchronous external abort. Add per-compatible data to the driver. Initially it contains the defer_utmi_clk_sel flag - set it for qcom,nord-dwc3 - which tells the driver to request an early PHY init from DWC3 core. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
The NE_GCC block has two eUSB2 PHY block resets - PRIM and SEC - but right now only the primary is registered. Add the secondary, which is required by the usb_1 eUSB2 PHY. Note that the SoC has three eUSB2 PHYs but only these two QUSB2PHY resets: the HS-only USB20 tile has no dedicated QUSB2PHY reset and is instead reset as a whole via NE_GCC_USB20_PRIM_BCR. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
Add the secondary USB2 PHY reset in order to enable the USB nodes in DTS for Nord Ride SX. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
The three eUSB2 PHY register ranges are reached through an AHB2PHY bridge in the NE_GCC tile. The bridge comes out of power-on with its block in reset asserted and its clock disabled. Nothing else on the SoC brings it up. Any access to a PHY config register in that state aborts with a synchronous external abort. Deassert the bridge reset and enable the clock in probe(). Mark the clock CLK_IGNORE_UNUSED so that clk_disable_unused() does not disable it again. No driver claims it as a consumer, since the bridge is transparent to the PHY drivers. Neither the reset nor the clock is exposed through the driver's reset/clock maps: doing so would let consumers control them individually, which is not how the hardware is meant to be used (the bridge must be up before any PHY driver can probe). Fixes: a4f780c ("clk: qcom: gcc: Add multiple global clock controller driver for Nord SoC") Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
We use the hw_clk_ctrl flag on six USB31 RCGs. Other Qualcomm GCC drivers do this for USB but on Nord the firmware does not bring the USB block out of reset nor drive the clock-request handshake. Drop hw_clk_ctrl from all six so the RCGs are driven purely from software Fixes: a4f780c ("clk: qcom: gcc: Add multiple global clock controller driver for Nord SoC") Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
ne_gcc_usb3_{prim,sec}_phy_aux_clk and _com_aux_clk never report
CLK_OFF=0 even with their RCG root running, so clk_branch_wait()
times out and the combo PHY fails to initialize.
Use BRANCH_HALT_SKIP for these four branches, as already done for the
pipe clocks in this driver.
Fixes: a4f780c ("clk: qcom: gcc: Add multiple global clock controller driver for Nord SoC")
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
Add the SPMI PMIC Arbiter node for the Nord platforms. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
Add the base nodes for the three DWC3 USB controllers. These carry only the SoC-invariant properties and are disabled by default. The extension for the embedded Nord variant and relevant board files will add the platform resources and enable them. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
…s and PHYs Add the platform resources for the USB controllers on the embedded Nord variant: clocks, resets, power domains and interconnect paths. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
Add the PMIC dtsi for Nord. Initially describe the two pmm8654au SPMI PMICs. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
Enable the USB controllers, their PHYs and wire up the repeaters. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
Enable USB_0 on the RRD board with PTN3222 eUSB2 redriver on I2C9. Although FUSB15201 Type-C controller driver is missing, enabling usb-role-switch and "otg" mode still make it easier to test both host and device mode, by manually switching the mode via: /sys/kernel/debug/usb/a600000.usb/mode Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Enable OTG mode for USB_0 so that ADB over USB can work. Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Enable Nord SoC USB_1 controller with the eUSB2 repeater and the onboard Genesys Logic GL3590 4-port USB 3.2 Gen1 hub as a peer-hub pair (usb5e3,610 HS die + usb5e3,625 SS die). Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Add device tree nodes to support ADSP (HPASS DSP) and CDSPs remoteproc on Nord SoC. This includes: - SMEM memory reservation used by the inter-processor communication infrastructure - IPCC mailbox controller for inter-processor signalling - AOSS QMP node for load state power management - SMP2P nodes providing stop control and fault/crash interrupt signals - Remoteproc nodes with a GLINK edge and FastRPC compute contexts for userspace offload The embedded variant specific power domains, XO clock, and interconnect paths are filled in nord-embedded.dtsi. Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Enable ADSP (HPASS DSP) and CDSPs remoteproc on the Nord RRD board. Due to a known issue, the first two or three CDSPs being probed may fail to boot up. A manual start can bring some of them out of reset. Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Enable ADSP (HPASS DSP) and CDSPs remoteproc on the Nord Ride Embedded board. Due to a known issue, the first two or three CDSPs being probed may fail to boot up. A manual start can bring some of them out of reset. Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Add device tree nodes to support ADSP1/2 which share HPASS clock/reset/NoC resources with ADSP0 and must boot after it. Give all three a qcom,cluster-root property so that they form one cluster which boots ADSP0 first and crashes or stops as a single unit. ADSP1/2 reference ADSP0, which owns those shared resources, and ADSP0 references itself, so that every member of the cluster declares its own membership rather than leaving the owner's implicit. Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Enable ADSP1 and ADSP2 remoteproc on the Nord RRD board. Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Enable ADSP1 and ADSP2 remoteproc the Nord Ride Embedded board. Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
QUP1 SE2 and SE3 pack all four of their lanes pair-wise onto only two pins each: lanes 0/1 (I2C SDA/SCL) at mux value 2 and lanes 2/3 (UART TX/RX) at mux value 1, on gpio127/gpio128 and gpio129/gpio130 respectively. Both mux values were named "qup1_se2" (respectively "qup1_se3"), so the two distinct lane pairs became indistinguishable. msm_pinmux_set_mux() stops at the first entry matching the requested function, which means mux value 1 was always selected and the I2C lanes could never be muxed out. In practice i2c9 and i2c10 got the UART lanes and did not work, while uart9 and uart10 happened to be muxed correctly. Give each lane pair its own function, following the _01/_23 naming already used for the same hardware arrangement by the shikra, eliza, hawi and maili TLMM drivers. Both functions still cover the full pin pair, so a single pinctrl state per protocol remains sufficient. While at it, drop gpio129/gpio130 from the SE2 group list; those pins belong to SE3 and were never reachable through the SE2 function. Fixes: c24dd08 ("pinctrl: qcom: add the TLMM driver for the Nord platforms") Cc: stable@vger.kernel.org Assisted-by: LLM Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
The i2c9/i2c10 and uart9/uart10 pinctrl states shared the same pins and the same "qup1_se2"/"qup1_se3" function name, so the I2C states were indistinguishable from the UART ones and ended up muxing the UART lanes. i2c9 and i2c10 therefore did not work. Now that the TLMM driver names each lane pair separately, select the lane 0/1 function for I2C and the lane 2/3 function for UART. Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Assign the I2C and SPI GENI SE power domains to the correct SCMI controllers (scmi9 for I2C, scmi10 for SPI) instead of scmi11, enable the scmi9 and scmi10 protocol nodes, and add the i2c18/spi16 aliases so the instances are enabled on nord. Signed-off-by: Aniket Randive <aniket.randive@oss.qualcomm.com>
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Assign the I2C and SPI GENI SE power domains to the correct SCMI
controllers (scmi9 for I2C, scmi10 for SPI) instead of scmi11, enable
the scmi9 and scmi10 protocol nodes, and add the i2c18/spi16 aliases so
the instances are enabled on nord.
Signed-off-by: Aniket Randive aniket.randive@oss.qualcomm.com