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@RISCV-LLM-Accelerator RISCV Accelerator

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    10 repositories

    • riscv-isa-sim

      Public
      Spike, a RISC-V ISA Simulator
      C
      •
      Other
      •1.1k•0•0•0•Updated Jul 3, 2025Jul 3, 2025

    • cva6

      Public
      The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
      Assembly
      •
      Other
      •1k•0•0•0•Updated Jul 3, 2025Jul 3, 2025

    • riscv-gnu-toolchain

      Public
      GNU toolchain for RISC-V, including GCC
      C
      •
      Other
      •1.4k•0•0•0•Updated Jul 3, 2025Jul 3, 2025

    • chipyard

      Public
      An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
      Scala
      •
      BSD 3-Clause "New" or "Revised" License
      •919•0•0•0•Updated Jun 30, 2025Jun 30, 2025

    • chipyard-micro-learning

      Public
      repository for chipyard micro learning course
      HTML
      •11•0•0•0•Updated Jun 20, 2025Jun 20, 2025

    • FireMarshal

      Public
      Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.
      Python
      •
      Other
      •72•0•0•0•Updated May 28, 2025May 28, 2025

    • rocket-chip

      Public
      Rocket Chip Generator
      Scala
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      Other
      •1.3k•0•0•0•Updated May 27, 2025May 27, 2025

    • hammer

      Public
      Hammer: Highly Agile Masks Made Effortlessly from RTL
      Python
      •
      BSD 3-Clause "New" or "Revised" License
      •80•0•0•0•Updated May 16, 2025May 16, 2025

    • riscv-boom

      Public
      SonicBOOM: The Berkeley Out-of-Order Machine
      Scala
      •
      BSD 3-Clause "New" or "Revised" License
      •530•0•0•0•Updated May 6, 2025May 6, 2025

    • gemmini

      Public
      Berkeley's Spatial Array Generator
      Scala
      •
      Other
      •295•0•0•0•Updated Apr 13, 2025Apr 13, 2025
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