decoder: enforce fixed-zero fields for HLV/HSV and CBO

[124107157-KV]

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Why is this PR needed?

The decoder currently accepts several reserved encodings where the ISA encoding requires particular instruction fields to be zero.

For the hypervisor load/store instructions, some unsupported rs2 values can pass through decode without setting illegal_instr, and the HSV encodings do not enforce the fixed-zero rd field.

Similarly, CBO.INVAL, CBO.CLEAN, and CBO.FLUSH do not currently enforce their fixed-zero rd field.

As a result, malformed encodings can proceed through the pipeline instead of raising an illegal-instruction exception.

What does this PR change?

This PR adds explicit decoder legality checks for the affected fixed fields.

For the HLV/HLVX instruction families:

• HLV.B/HLV.BU only accept rs2 = 0 or rs2 = 1.
• HLV.H/HLV.HU/HLVX.HU only accept rs2 = 0, 1, or 3.
• HLV.W/HLV.WU/HLVX.WU only accept rs2 = 0, 1, or 3.
• HLV.D requires rs2 = 0.
• Any other rs2 encoding in these instruction families is marked illegal.

For HSV:

• HSV.B, HSV.H, HSV.W, and HSV.D now require the encoded rd field to be zero.
• A non-zero rd is marked illegal.

For the cache-block operations:

• CBO.INVAL, CBO.CLEAN, and CBO.FLUSH now require the encoded rd field to be zero.
• A non-zero rd is marked illegal before the CBO operation is selected.

Verification

Two directed assembly regressions were added:

• decoder-hlv-hsv-fixed-fields-rv64
• decoder-cbo-rd-zero-rv64

The HLV/HLVX/HSV regression uses raw instruction encodings covering:

• reserved HLV.B/BU rs2
• reserved HLV.H/HU/HLVX.HU rs2
• reserved HLV.W/WU/HLVX.WU rs2
• non-zero HLV.D rs2
• non-zero HSV.B/H/W/D rd

Each malformed encoding is expected to raise an illegal-instruction exception with mcause = 2.

The CBO regression checks CBO.INVAL, CBO.CLEAN, and CBO.FLUSH with non-zero rd, with each encoding expected to raise mcause = 2.

The regressions were also added to verif/regress/issue-tests.sh.

HLV/HLVX/HSV

Target:

cv64a6_imafdch_sv39

Original decoder:

RED_H=1

Patched decoder:

GREEN_H=0

CBO.INVAL/CLEAN/FLUSH

Target:

cv64a6_imafdc_sv39_hpdcache

Original decoder:

RED_CBO=1

Patched decoder:

GREEN_CBO=0

Both directed tests also compile successfully with the RISC-V GCC toolchain, and the expected malformed raw instruction encodings were verified in the generated ELF files.

Limitations

This change only adds the missing decoder legality checks for the fixed fields reported in the issue. It does not change the execution semantics of any valid HLV, HLVX, HSV, or CBO instruction encoding.

Fixes #3463