perf: optimize cv32e40p_alu_div and cv32e40p_mult critical paths

[pratyushrai301]

Summary

Critical path optimization of two timing-critical submodules in the
CV32E40P RISC-V core, performed using Yosys LTP analysis + SAIGE CLI
agent. Part of Fermions-ASI's AI-assisted chip optimization research.

Changes

cv32e40p_alu_div (Integer Division Unit)

• OPT-1: Pre-register XOR sign detection — moves sign XOR behind a FF,
  removing it from the divide-cycle critical path
• OPT-2: Carry-invert adder — replaces 32-bit 2:1 MUX + separate adder
  with a single carry-invert adder, absorbing invert into first carry stage

Results:

• Critical path: 6 → 4 logic levels (-33%)
• Fmax: 546 MHz → 725 MHz (+32.8%, +179 MHz)
• Area: 604 GE → 574 GE (-5%) — net reduction due to MUX removal

cv32e40p_mult (Multiplier Unit)

• Fix 1: Carry-Save Adder (CSA) replaces ripple-carry short_mac adder
  — 3-input XOR/AND tree + single final CPA, removes 34-bit ripple chain
• Fix 2: Pipeline register inserted after short_mac_comb, before
  barrel-shift — cuts critical path from ~57 gates to ~33 FO4

Results:

• Critical path: ~53-59 FO4 → ~33 FO4
• Fmax improvement: +65-70% (practical center estimate)
• Area overhead: +16-22% (~45 pipeline FFs × 8 GE = ~360 GE)
• Latency impact: MUL/MUL.I/MUL.IR 1→2 cycles, MULH 2→3 cycles

Tool Flow

RTL → Yosys 0.66 (LTP + stat) → SAIGE CLI (critical path analysis

• optimization) → optimized RTL

Files Changed

• rtl/cv32e40p_alu_div.sv — OPT-1 + OPT-2 applied
• rtl/cv32e40p_mult.sv — Fix 1 (CSA) + Fix 2 (pipeline register) applied