Cv32e40s/dev -> master by silabs-hfegran · Pull Request #2257 · openhwfoundation/core-v-verif

silabs-hfegran · 2023-10-23T12:36:48Z

No description provided.

Signed-off-by: Henrik Fegran <Henrik.Fegran@silabs.com>

…CLIC_INTTHRESHBITS remove CLIC_INTTHRESHBITS

Signed-off-by: Henrik Fegran <Henrik.Fegran@silabs.com>

Signed-off-by: Marton Teilgard <mateilga@silabs.com>

…sert_mtvt_fields fixed struct mtvt_t to work with small id widths

…dgen_bugfix cv32e40s ldgen bugfix

Signed-off-by: Henrik Fegran <Henrik.Fegran@silabs.com>

…alized Update "x/dev"

…egression_script_noiss_fix Updated regression scripts to fix issues with --iss 0

…e after latest changes Signed-off-by: Henrik Fegran <Henrik.Fegran@silabs.com>

…emove_b_abs_cfg Removed b_ext_abs cfg from b-ext test in full regression

Signed-off-by: Kristine Dosvik <krdosvik@silabs.com>

use hash=709bec4 instead of main in clonetb

…to xdev_merge_in_sdev Signed-off-by: Kristine Dosvik <krdosvik@silabs.com>

Signed-off-by: Marton Teilgard <mateilga@silabs.com>

Signed-off-by: Kristine Dosvik <krdosvik@silabs.com>

…rge_in_sdev Xdev merge in sdev

Signed-off-by: Kristine Dosvik <krdosvik@silabs.com>

Signed-off-by: Ingrid Haahjem <Ingrid.Haahjem@silabs.com>

…cv32e40x cv32e40x contains only a readme

…-into-s Merge x into s

Signed-off-by: Ingrid Haahjem <Ingrid.Haahjem@silabs.com>

… build_asm Signed-off-by: Ingrid Haahjem <Ingrid.Haahjem@silabs.com>

…mbler_updates Added Zc* instructions to disassembler

Signed-off-by: Henrik Fegran <Henrik.Fegran@silabs.com>

Signed-off-by: Robin Pedersen <Robin.Pedersen@silabs.com>

…n_update Updated link to coverage

Directed Test - Pushpop Debug Triggers

Signed-off-by: Robin Pedersen <Robin.Pedersen@silabs.com>

…to secureseed_tmp Signed-off-by: Robin Pedersen <Robin.Pedersen@silabs.com>

Signed-off-by: Robin Pedersen <Robin.Pedersen@silabs.com>

Directed Tests - `secureseed`

Signed-off-by: Henrik Fegran <Henrik.Fegran@silabs.com>

…sa_decoder_fix Added compressed csr-representation to isa decoder

…ss explicitly specified Signed-off-by: Henrik Fegran <Henrik.Fegran@silabs.com>

… to fix ISS coverage issue Signed-off-by: Henrik Fegran <Henrik.Fegran@silabs.com>

Signed-off-by: Henrik Fegran <Henrik.Fegran@silabs.com>

…ocsf_flag Added flag to prevent xcelium from searching for cds.lib/hdl.var

…fe_test_updates Updated wfe test to work correctly without user-mode/PMP, added flags…

MikeOpenHWGroup · 2023-10-23T13:03:12Z

Thanks for opennng this PR @silabs-hfegran. At this point, the merge conflicts don't look too bad:

$ git merge silabs-hfegran/cv32e40s/dev
Auto-merging bin/ci_check
Auto-merging cv32e40p/sim/ExternalRepos.mk
CONFLICT (modify/delete): cva6/tb/uvmt/uvmt_cva6_dut_wrap.sv deleted in HEAD and modified in silabs-hfegran/cv32e40s/dev.  Version silabs-hfegran/cv32e40s/dev of cva6/tb/uvmt/uvmt_cva6_dut_wrap.sv left in tree.
CONFLICT (modify/delete): cva6/tb/uvmt/uvmt_cva6_tb.sv deleted in HEAD and modified in silabs-hfegran/cv32e40s/dev.  Version silabs-hfegran/cv32e40s/dev of cva6/tb/uvmt/uvmt_cva6_tb.sv left in tree.
Auto-merging lib/uvm_agents/uvma_isacov/uvma_isacov_mon.sv
CONFLICT (content): Merge conflict in lib/uvm_agents/uvma_isacov/uvma_isacov_mon.sv
Auto-merging lib/uvm_agents/uvma_obi_memory/src/comps/uvma_obi_memory_cov_model.sv
Auto-merging lib/uvm_agents/uvma_rvfi/uvma_rvfi_instr_mon.sv
Auto-merging mk/Common.mk
Automatic merge failed; fix conflicts and then commit the result.

So, "only" three conflicts. I'll take a look and report back.

silabs-hfegran · 2023-10-23T13:29:42Z

Thanks for opennng this PR @silabs-hfegran. At this point, the merge conflicts don't look too bad:

$ git merge silabs-hfegran/cv32e40s/dev
Auto-merging bin/ci_check
Auto-merging cv32e40p/sim/ExternalRepos.mk
CONFLICT (modify/delete): cva6/tb/uvmt/uvmt_cva6_dut_wrap.sv deleted in HEAD and modified in silabs-hfegran/cv32e40s/dev.  Version silabs-hfegran/cv32e40s/dev of cva6/tb/uvmt/uvmt_cva6_dut_wrap.sv left in tree.
CONFLICT (modify/delete): cva6/tb/uvmt/uvmt_cva6_tb.sv deleted in HEAD and modified in silabs-hfegran/cv32e40s/dev.  Version silabs-hfegran/cv32e40s/dev of cva6/tb/uvmt/uvmt_cva6_tb.sv left in tree.
Auto-merging lib/uvm_agents/uvma_isacov/uvma_isacov_mon.sv
CONFLICT (content): Merge conflict in lib/uvm_agents/uvma_isacov/uvma_isacov_mon.sv
Auto-merging lib/uvm_agents/uvma_obi_memory/src/comps/uvma_obi_memory_cov_model.sv
Auto-merging lib/uvm_agents/uvma_rvfi/uvma_rvfi_instr_mon.sv
Auto-merging mk/Common.mk
Automatic merge failed; fix conflicts and then commit the result.

So, "only" three conflicts. I'll take a look and report back.

Two deleted files, and one actual conflict - shouldn't be too hard to fix, but my first attempt failed to run hello-world.

Signed-off-by: Henrik Fegran <Henrik.Fegran@silabs.com>

silabs-hfegran · 2023-10-23T13:57:33Z

Merge conflicts should be OK now, runs hello world, but I will need some time to run a larger regression

MikeOpenHWGroup · 2023-10-23T14:32:00Z

Update on the three conflicts. The first two are easy: the cva6 directory has been deleted from CORE-V-VERIF, so cva6/tb/uvmt/uvmt_cva6_dut_wrap.sv and cva6/tb/uvmt/uvmt_cva6_tb.sv can safely be deleted here.

The last one, lib/uvm_agents/uvma_isacov/uvma_isacov_mon.sv is more challenging. Below is a snipit of the conflict. I believe we want to deleted the HEAD section (everything between <<<<<<< HEAD and =======) and keep silabs-hfegran/cv32e40s/dev (everything from ======= and >>>>>>> silabs-hfegran/cv32e40s/dev).

Comments?

<<<<<<< HEAD
  // Disassemble the instruction using Spike (via DPI)
  if (mon_trn.instr.ext == C_EXT) begin
    mon_trn.instr.rs1     = dasm_rvc_rs1(instr);
    mon_trn.instr.rs2     = dasm_rvc_rs2(instr);
    mon_trn.instr.rd      = dasm_rvc_rd(instr);
    mon_trn.instr.c_rdrs1 = dasm_rvc_rd(instr);
    mon_trn.instr.c_rd    = mon_trn.instr.decode_rd_c(instr);
    mon_trn.instr.c_rs1   = mon_trn.instr.decode_rs1_c(instr);
    mon_trn.instr.c_rs2   = mon_trn.instr.decode_rs2_c(instr);
  end
  else begin
    mon_trn.instr.rs1  = dasm_rs1(instr);
    mon_trn.instr.rs2  = dasm_rs2(instr);
    mon_trn.instr.rd   = dasm_rd(instr);
    mon_trn.instr.immi = dasm_i_imm(instr);
    mon_trn.instr.imms = dasm_s_imm(instr);
    mon_trn.instr.immb = dasm_sb_imm(instr) >> 1;  // Because dasm gives [12:0], not [12: 1]
    mon_trn.instr.immu = dasm_u_imm(instr) >> 12;  // Because dasm gives [31:0], not [31:12]
    mon_trn.instr.immj = dasm_uj_imm(instr) >> 1;  // Because dasm gives [20:0], not [20: 1]
=======
    //Disassemble the instruction using Spike (via DPI)
    if (mon_trn.instr.ext == C_EXT) begin
      mon_trn.instr.rs1     = dasm_rvc_rs1(instr);
      mon_trn.instr.rs2     = dasm_rvc_rs2(instr);
      mon_trn.instr.rd      = dasm_rvc_rd(instr);
      mon_trn.instr.c_rdrs1 = dasm_rvc_rd(instr);
      mon_trn.instr.c_rdp   = dasm_rvc_rs1s(instr);
      mon_trn.instr.c_rs1s  = dasm_rvc_rs1s(instr);
      mon_trn.instr.c_rs2s  = dasm_rvc_rs2s(instr);
    end
    else begin
      mon_trn.instr.rs1  = dasm_rs1(instr);
      mon_trn.instr.rs2  = dasm_rs2(instr);
      mon_trn.instr.rd   = dasm_rd(instr);
      mon_trn.instr.immi = dasm_i_imm(instr);
      mon_trn.instr.imms = dasm_s_imm(instr);
      mon_trn.instr.immb = dasm_sb_imm(instr) >> 1;  // Because dasm gives [12:0], not [12: 1]
      mon_trn.instr.immu = dasm_u_imm(instr) >> 12;  // Because dasm gives [31:0], not [31:12]
      mon_trn.instr.immj = dasm_uj_imm(instr) >> 1;  // Because dasm gives [20:0], not [20: 1]
    end

    // Make instructions as illegal,
    // 1. If a CSR instruction is not targeted to a valid CSR
    if (mon_trn.instr.group == CSR_GROUP) begin
      mon_trn.instr.csr_val = dasm_csr(instr);
      if (!$cast(mon_trn.instr.csr, mon_trn.instr.csr_val) ||
           cfg.core_cfg.unsupported_csr_mask[mon_trn.instr.csr_val]) begin
        mon_trn.instr.illegal = 1;
      end
    end

  end else if (cfg.decoder == ISA_SUPPORT) begin
    // Attempt to decode instruction with isa_support

    // TODO: silabs-hefegran, isa decoder representation changed for compressed 'rx registers,
    // we supply the old (non-translated) value to avoid having to rewrite that logic now, which
    // might also interfere with the spike implementation.
    // the "get_rx"-functions should no longer be needed if we supply the translated values to
    // the coverage model.
    mon_trn.instr.c_rdrs1 = instr_asm.rd.valid_gpr_rvc  ? instr_asm.rd.gpr_rvc  : instr_asm.rd.gpr;
    mon_trn.instr.c_rdp   = instr_asm.rd.valid_gpr_rvc  ? instr_asm.rd.gpr_rvc  : instr_asm.rd.gpr;
    mon_trn.instr.c_rs1s  = instr_asm.rs1.valid_gpr_rvc ? instr_asm.rs1.gpr_rvc : instr_asm.rs1.gpr;
    mon_trn.instr.c_rs2s  = instr_asm.rs2.valid_gpr_rvc ? instr_asm.rs2.gpr_rvc : instr_asm.rs2.gpr;
    mon_trn.instr.rs1     = instr_asm.rs1.valid_gpr_rvc ? instr_asm.rs1.gpr_rvc : instr_asm.rs1.gpr;
    mon_trn.instr.rs2     = instr_asm.rs2.valid_gpr_rvc ? instr_asm.rs2.gpr_rvc : instr_asm.rs1.gpr;
    mon_trn.instr.rd      = instr_asm.rd.valid_gpr_rvc  ? instr_asm.rd.gpr_rvc  : instr_asm.rd.gpr;
    mon_trn.instr.immi    = instr_asm.imm.imm_raw_sorted;
    mon_trn.instr.imms    = instr_asm.imm.imm_raw_sorted;
    mon_trn.instr.immb    = instr_asm.imm.imm_raw_sorted;
    mon_trn.instr.immu    = instr_asm.imm.imm_raw_sorted;
    mon_trn.instr.immj    = instr_asm.imm.imm_raw_sorted;

    // Make instructions as illegal,
    // 1. If a CSR instruction is not targeted to a valid CSR
    if (mon_trn.instr.group == CSR_GROUP) begin
      mon_trn.instr.csr_val = instr_asm.csr.address;
      if (!$cast(mon_trn.instr.csr, mon_trn.instr.csr_val) ||
           cfg.core_cfg.unsupported_csr_mask[mon_trn.instr.csr_val]) begin
        mon_trn.instr.illegal = 1;
      end
    end
>>>>>>> silabs-hfegran/cv32e40s/dev
  end

silabs-hfegran · 2023-10-24T07:02:27Z

Update on the three conflicts. The first two are easy: the cva6 directory has been deleted from CORE-V-VERIF, so cva6/tb/uvmt/uvmt_cva6_dut_wrap.sv and cva6/tb/uvmt/uvmt_cva6_tb.sv can safely be deleted here.

The last one, lib/uvm_agents/uvma_isacov/uvma_isacov_mon.sv is more challenging. Below is a snipit of the conflict. I believe we want to deleted the HEAD section (everything between <<<<<<< HEAD and =======) and keep silabs-hfegran/cv32e40s/dev (everything from ======= and >>>>>>> silabs-hfegran/cv32e40s/dev).

Comments?

Close, there are some changes from HEAD that needs to be included, for example this part:

    mon_trn.instr.c_rd    = mon_trn.instr.decode_rd_c(instr);
    mon_trn.instr.c_rs1   = mon_trn.instr.decode_rs1_c(instr);
    mon_trn.instr.c_rs2   = mon_trn.instr.decode_rs2_c(instr);

There are also a couple of naming changes where rdp, rs1s and rs2s are renamed to rd, rs1 and rs2 respectively. c.f. my latest fix. I ran this through full regressions overnight and it appears to give me more or less same results as for the 40s/dev branch, additionally isacov coverage looks as expected. I will go ahead and convert this to a proper PR as it looks good from our point of view.

silabs-hfegran · 2023-10-30T09:20:33Z

@MikeOpenHWGroup: Are we waiting for someone/something before merging this?

MikeOpenHWGroup · 2023-10-30T13:21:50Z

@MikeOpenHWGroup: Are we waiting for someone/something before merging this?

I had the same question this morning. :-) I'm running a few tests and will approve (or not) based on their outcome.

silabs-hfegran and others added 30 commits June 29, 2023 13:25

Fixed errors+cleanup in uvma_pma_sb

eea7704

Signed-off-by: Henrik Fegran <Henrik.Fegran@silabs.com>

Fixed missing return statement

2c8410e

Signed-off-by: Henrik Fegran <Henrik.Fegran@silabs.com>

Merge pull request openhwfoundation#2010 from silabs-krdosvik/remove_…

1556968

…CLIC_INTTHRESHBITS remove CLIC_INTTHRESHBITS

Fixed debug_priv_test issue with word load/store for byte variable

34976af

Signed-off-by: Henrik Fegran <Henrik.Fegran@silabs.com>

fixed struct mtvt_t to work with small id widths

80a6d57

Signed-off-by: Marton Teilgard <mateilga@silabs.com>

Merge pull request openhwfoundation#2024 from silabs-mateilga/clic_as…

c04d577

…sert_mtvt_fields fixed struct mtvt_t to work with small id widths

Merge pull request openhwfoundation#1991 from silabs-hfegran/dev_hf_l…

64209a9

…dgen_bugfix cv32e40s ldgen bugfix

Updated regression scripts to fix issues with --iss 0

2764c92

Signed-off-by: Henrik Fegran <Henrik.Fegran@silabs.com>

Merge pull request openhwfoundation#2025 from silabs-robin/xdev_revit…

4c23abf

…alized Update "x/dev"

Merge pull request openhwfoundation#2026 from silabs-hfegran/dev_hf_r…

3b12420

…egression_script_noiss_fix Updated regression scripts to fix issues with --iss 0

Removed b_ext_abs cfg from b-ext test in full regression (incompatibl…

bbcffd6

…e after latest changes Signed-off-by: Henrik Fegran <Henrik.Fegran@silabs.com>

Merge pull request openhwfoundation#2027 from silabs-hfegran/dev_hf_r…

1766deb

…emove_b_abs_cfg Removed b_ext_abs cfg from b-ext test in full regression

use hash=709bec4 instead of main in clonetb

7e3d444

Signed-off-by: Kristine Dosvik <krdosvik@silabs.com>

Merge pull request openhwfoundation#2030 from silabs-krdosvik/new_b

4e8836a

use hash=709bec4 instead of main in clonetb

Merge branch 'cv32e40s/dev' of github.com:openhwgroup/core-v-verif in…

d1f528d

…to xdev_merge_in_sdev Signed-off-by: Kristine Dosvik <krdosvik@silabs.com>

unfinished clic asserts disabled, wip

b91d76f

Signed-off-by: Marton Teilgard <mateilga@silabs.com>

update to correct hash in bin/clonetb

ed18a97

Signed-off-by: Kristine Dosvik <krdosvik@silabs.com>

Merge pull request openhwfoundation#2031 from silabs-krdosvik/xdev_me…

40f77e7

…rge_in_sdev Xdev merge in sdev

cv32e40x contains only a readme

926329f

Signed-off-by: Kristine Dosvik <krdosvik@silabs.com>

Added Zc* instructions to disassembler

f207535

Signed-off-by: Ingrid Haahjem <Ingrid.Haahjem@silabs.com>

Merge pull request openhwfoundation#2036 from silabs-krdosvik/delete-…

e8e1a85

…cv32e40x cv32e40x contains only a readme

Merge pull request openhwfoundation#2038 from silabs-krdosvik/merge-x…

6606805

…-into-s Merge x into s

Updates on hint functions and removed forgotten comments

8f3f3a5

Signed-off-by: Ingrid Haahjem <Ingrid.Haahjem@silabs.com>

updated get_stack_adj function to use case statement with inside

3cfa633

Signed-off-by: Ingrid Haahjem <Ingrid.Haahjem@silabs.com>

Made enums of funct3 and funct5

5d14856

Signed-off-by: Ingrid Haahjem <Ingrid.Haahjem@silabs.com>

removed signals set to default value in build_asm function

40a9b9b

Signed-off-by: Ingrid Haahjem <Ingrid.Haahjem@silabs.com>

Removed signals set to default value(0) also on first if statement of…

7b800ad

… build_asm Signed-off-by: Ingrid Haahjem <Ingrid.Haahjem@silabs.com>

Merge pull request openhwfoundation#2037 from silabs-inhaahje/disasse…

4db547f

…mbler_updates Added Zc* instructions to disassembler

Added clic tests to cover coverage holes, fixed clic test issues

121c195

Signed-off-by: Henrik Fegran <Henrik.Fegran@silabs.com>

Removed superfluous typecast of constant

a35cf07

Signed-off-by: Henrik Fegran <Henrik.Fegran@silabs.com>

silabs-robin and others added 17 commits October 18, 2023 16:59

test pop debug triggers

cc35f7d

Signed-off-by: Robin Pedersen <Robin.Pedersen@silabs.com>

move pushpop test to standalone

9d39f43

Signed-off-by: Robin Pedersen <Robin.Pedersen@silabs.com>

Merge pull request openhwfoundation#2248 from silabs-mateilga/zc_vpla…

2397993

…n_update Updated link to coverage

Merge pull request openhwfoundation#2253 from silabs-robin/wpt_pushpop

24e9ad2

Directed Test - Pushpop Debug Triggers

merge 'secureseed' test into 'xsecure_csrs' test

2e90d8c

Signed-off-by: Robin Pedersen <Robin.Pedersen@silabs.com>

Merge branch 'cv32e40s/dev' of github.com:openhwgroup/core-v-verif in…

fd3618a

…to secureseed_tmp Signed-off-by: Robin Pedersen <Robin.Pedersen@silabs.com>

add vplan item for future complete checking of lfsr lockup

70800b4

Signed-off-by: Robin Pedersen <Robin.Pedersen@silabs.com>

add comment about missing lfsr lockup check

8c344c0

Signed-off-by: Robin Pedersen <Robin.Pedersen@silabs.com>

Merge pull request openhwfoundation#2239 from silabs-robin/secureseed

30cdc51

Directed Tests - `secureseed`

Name changes to compressed register representations

62b3768

Signed-off-by: Henrik Fegran <Henrik.Fegran@silabs.com>

Another name change, cleanup, add default case

f494abd

Signed-off-by: Henrik Fegran <Henrik.Fegran@silabs.com>

Merge pull request openhwfoundation#2251 from silabs-hfegran/dev_hf_i…

3470297

…sa_decoder_fix Added compressed csr-representation to isa decoder

Added flag to prevent xcelium from searching for cds.lib/hdl.var unle…

538a401

…ss explicitly specified Signed-off-by: Henrik Fegran <Henrik.Fegran@silabs.com>

Updated wfe test to work correctly without user-mode/PMP, added flags…

457d2e9

… to fix ISS coverage issue Signed-off-by: Henrik Fegran <Henrik.Fegran@silabs.com>

Reverted ISS flag as it appeared to have no effect

e6db7d8

Signed-off-by: Henrik Fegran <Henrik.Fegran@silabs.com>

Merge pull request openhwfoundation#2254 from silabs-hfegran/dev_hf_n…

99767cd

…ocsf_flag Added flag to prevent xcelium from searching for cds.lib/hdl.var

Merge pull request openhwfoundation#2255 from silabs-hfegran/dev_hf_w…

7c2a400

…fe_test_updates Updated wfe test to work correctly without user-mode/PMP, added flags…

silabs-hfegran requested a review from MikeOpenHWGroup October 23, 2023 12:36

Merge branch 'cv32e40s/dev' of github.com:silabs-hfegran/core-v-verif

af0b537

Fix merge conflicts

a45b7ea

Signed-off-by: Henrik Fegran <Henrik.Fegran@silabs.com>

silabs-hfegran marked this pull request as ready for review October 24, 2023 07:02

AyoubJalali mentioned this pull request Oct 26, 2023

[TASK] Add coverage dedicated to Zce to ISACOV openhwfoundation/cva6#1398

Open

MikeOpenHWGroup added the cv32e40s label Nov 27, 2023

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Cv32e40s/dev -> master - #2257

Cv32e40s/dev -> master#2257
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