subsys: reduce flash operations during ZBOSS NVRAM storage - #141
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nvram_flash_write() issued a separate flash_area_write() for every flash write block, even when the data was aligned and contiguous. Storing a typical ZBOSS dataset therefore required many flash operations. Read-modify-write only the unaligned head and tail block and write the aligned middle in a single operation. The bytes written are unchanged, so this is transparent to ZBOSS. Verified on nRF54L15 by storing a network and restoring it after reset. Signed-off-by: Eduardo Montoya <eduardo.montoya@nordicsemi.no>
ZBOSS stores a dataset through many small consecutive zb_osif_nvram_write() calls and marks the end of the dataset with zb_osif_nvram_flush(). Each call previously reached flash separately, which made NVRAM storage slow. Gather writes that continue the cached range in RAM and commit them as one flash operation when ZBOSS flushes the dataset. Also commit before an erase, before a read so a reader always sees its own data, and from zb_osif_nvram_wait_for_last_op(). Writes that do not continue the range, and writes larger than the cache, commit what is pending first, so the bytes reaching flash and their order are unchanged. The cache is sized by CONFIG_ZIGBEE_NVRAM_WRITE_CACHE_SIZE and defaults to 512 bytes. Set it to 0 to disable the cache and write directly to flash. On multiprotocol SoCs where flash access is less contended, the default is 0. Signed-off-by: Eduardo Montoya <eduardo.montoya@nordicsemi.no>
Signed-off-by: Eduardo Montoya <eduardo.montoya@nordicsemi.no>
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All path_triggers must point to the samples and boards that have defined integration_platforms entry. Signed-off-by: Arkadiusz Balys <arkadiusz.balys@nordicsemi.no>
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ZBOSS NVRAM storage issued too many small flash writes. This PR cuts that down in two ways:
nvram_flash_write()— write the aligned middle of a buffer in oneflash_area_write(), only the unaligned head and tail use read-modify-write.zb_osif_nvram_write()calls and commit them onzb_osif_nvram_flush().Flash content and write order are unchanged. Cache size is controlled by
CONFIG_ZIGBEE_NVRAM_WRITE_CACHE_SIZE(default 512 B; 0 on multiprotocol SoCs where flash is less contended).