Computer Engineering student at the University of São Paulo (USP) and undergraduate researcher at CITI-USP.
I am interested in computer architecture, RISC-V, digital hardware, and hardware/software co-design. My current undergraduate research focuses on heterogeneous Edge AI systems, studying workload-to-architecture mapping, data types, parallelism, memory behavior, and RISC-V-based architectures.
I am particularly interested in FPGA/reconfigurable architectures, accelerators, and efficient ML systems.
CITI-USP — Heterogeneous Edge AI HW–SW co-design
Exploring workload mapping and architectural trade-offs around PULP/Snitch, Spatz, and Deeploy, with emphasis on parallelism, data movement, memory behavior, and efficient inference.
- Personal RV32I Single-Cycle Processor — modular Verilog/SystemVerilog core, end-to-end assembly verification (55/55 checks), and Yosys synthesis/area characterization.
- IEEE-754 Single-Precision FPU — synchronous binary32 FPU with arithmetic, comparison, flags, and integrated verification.
- RISC-V 32-bit ALU — personal RTL ALU with module-level self-checking verification.
- Digital Design Labs — Verilog and RISC-V work covering UART TX/RX, Wishbone system integration, memory design, arithmetic circuits, and assembly.
- Algorithms & Performance Analysis — C data structures, graph algorithms, and a Dijkstra priority-queue performance study.
- Autonomous Drone Vision & Mission Control — OpenCV perception and mission-control work from SkyRats.
- SymbolGame Embedded Console — Raspberry Pi console for symbol-supported interactive storytelling.