All pull requests

Pull requests

• [proj] D1 sign-off for tag controller

  #743·marnovandermaas opened Sep 22, 2026Collaborator·

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  19

• [proj] Debug Module D1 sign-off

  #741·PRugg-Cap opened Sep 18, 2026·

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  15

• [proj] AXI crossbar D1 sign-off

  #740·tchilikov-semify opened Sep 17, 2026Collaborator·

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  1

  18

• [proj] CVA6-CHERI D1 sign-off

  #738·PRugg-Cap opened Sep 16, 2026·

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  33

• [proj] Mailbox D1 sign-off

  #737·tchilikov-semify opened Sep 16, 2026Collaborator·

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  1

  7

• [proj] Timer D1 sign-off

  #726·tchilikov-semify opened Sep 11, 2026Collaborator·

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  1

  5

• [proj] SPI device D1 sign-off

  #725·tchilikov-semify opened Sep 11, 2026Collaborator·

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  1

  5

• [dv,kmac] add a top-level KMAC smoke test

  #701·tchilikov-semify opened Aug 26, 2026Collaborator·

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  1

• [dv] V1 signoff for SPI Host DV block

  #700·tchilikov-semify opened Aug 25, 2026Collaborator·

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  1

• [dv] V1 signoff for SPI Device DV block

  #699·tchilikov-semify opened Aug 20, 2026Collaborator·

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  1

• [dv,clk_mgr] Vendor in clk_mgr DV environment from OT

  #698·tchilikov-semify opened Aug 20, 2026Collaborator·

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  1

  2

• [dv,sram] Update SRAM vPlan with Metric Types

  #697·tchilikov-semify opened Aug 18, 2026Collaborator·

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  10

• Integrate new Ethernet

  #693·thomas6785 opened Jul 29, 2026·

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  4

• [rtl] Refactor mem_downsizer for full throughput + min latency

  #692·thomas6785 opened Jul 28, 2026·

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• [util] FPGA resource utilisation reporting + visualiser utility

  #691·thomas6785 opened Jul 27, 2026·

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  9

• AXI4 VIP development and integration

  #688·tchilikov-semify opened Jul 22, 2026Collaborator·

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  1

  212

• [fpga] Add clock constraints for SPI device

  #681·raylau1 opened Jul 14, 2026Contributor·

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  1

  1

  

• [top,dv] Add testplan for top-level

  #668·martin-velay opened Jul 10, 2026Contributor·

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  1

  35

• [doc] Release timeline adjustments

  #643·marnovandermaas opened Jun 25, 2026Collaborator·

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• [i2c, dv] I2C V1 sign-off

  #616·KinzaQamar opened Jun 17, 2026Contributor·

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  1

  28

• [hw] Split DV and DD for lowRISC vendored IPs

  #612·martin-velay opened Jun 16, 2026Contributor·

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  9

• [dv] V1 signoff for GPIO block

  #611·martin-velay opened Jun 16, 2026Contributor·

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  23

• [clkmgr, dv] Clock Manager DV ported to Mocha

  #560·KolosKoblasz-Semify opened May 18, 2026Contributor·

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  1

• [DRAFT] spi_device hal refactor

  #551·engdoreis opened May 13, 2026Collaborator·

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• [util] Improve the verilator runner to capture traces

  #519·engdoreis opened May 1, 2026Collaborator·

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