feat(cuda): TexTable — layered 1-D lookup-table textures with point/hardware filtering - #24
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…ardware filtering
Immutable layered 1-D float32 tables evaluated by piecewise-linear
interpolation at grid-space coordinates, backed by a layered cudaArray +
cudaTextureObject_t on the CUDA build and a host-memory parity stub by
default. Two filter modes fixed at construction: point (two point fetches
+ explicit contraction-blocked float32 lerp, bit-identical between the
CUDA kernel and the CPU stub) and hardware linear (zero-ALU texture-unit
lerp with CUDA's 9-bit fixed-point weight, tolerance-validated; the stub
emulates the quantized weight).
- csrc/cuda/common/torchlean_cuda_textable.h: boxed ABI + symbol contract
- csrc/cuda/textures/torchlean_cuda_textable{.cu,_stub.c}: external class,
layered-array construction, fetch kernel/loop, metadata accessors
- lakefile: extern_lib torchlean_cuda_textable via buildNativeBackendLib
- Cuda.Trusted: opaque TexTable handle; Cuda.TexTable: extern bindings
- Cuda.KernelSpec: texLerpSpec (point-mode lerp over decomposed indices)
- Tests/Runtime/Cuda/TexTable: bit-exact point mode vs an executable
Float32 reference, tolerance-gated hardware mode, integer-node
texel-center probes, clamp/width=1/empty edges; wired into the suite
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TexTable.ofFloatArray data width layers hwFilterbuilds an immutable layered 1-D float32 table;TexTable.fetch tbl coords layerIdxevaluates piecewise-linear interpolation at grid-space coordinatesu ∈ [0, width−1](clamp addressing; the+0.5texel-center offset is handled internally) in one launch over the existingBuffermarshaling path. On the CUDA build the table is a layeredcudaArraybound once to acudaTextureObject_t; the default build ships a host-memory parity stub, solake buildstays green without a GPU.Two filter modes, fixed at construction:
__fadd_rn/__fmul_rn/__fsub_rn) float32 lerp — bit-identical between the CUDA kernel and the CPU stub. (The native backend compiles without--fmad=false, so FMA is blocked by intrinsics, not flags.)tex1DLayeredfiltered fetch — zero-ALU lerp using the texture unit's 9-bit fixed-point weight, tolerance-validated (CUDA does not specify coefficient rounding); the stub emulates the quantized weight.Motivation
Small tabulated transfer functions — calibration curves, inverted sensor-response tables, activation LUTs — are read-only, reused across many launches, and small enough to stay texture-cache resident. Binding one as a texture object turns a gather that would otherwise be a multi-launch composed pipeline into a single fetch per element. The op is forward-only by design (no autograd node); the lerp-slope backward is well-defined future work.
Tests
NN/Tests/Runtime/Cuda/TexTable.lean(wired into the CUDA coverage suite): point mode bit-exact vs the executabletexLerpSpecreference — compared byFloat.toBits, not a tolerance; hardware mode within the 9-bit-weight bound of the unquantized reference; integer-node texel-center probes exact in both modes (catches ±0.5 coordinate errors); clamp-below/above,width = 1, multi-layer, and empty-coords edges. Like the rest of the suite it runs on the CPU stub (lake build) and on the GPU (-K cuda) alike.Verification
nvcccompiles the kernel TU;cccompiles the stub; the@[extern]bindings elaborate; both TUs export the same symbol set so the default build links.nn_tests_suiteis green on the CPU stub and with-K cuda=trueon an RTX A4500; the point-mode stub↔GPU bit-identity holds on real texture hardware, and the texel-center probes pass under both filter modes.