How to silence log output during `evaluateCircuit`

Despite setting `interpreterOptions.verbose = false`, running even the example in the readme results in the [`CircuitState` being printed](https://github.com/freechipsproject/firrtl-interpreter/blob/4103e92011c3fa82c9f95fc42bf27d2d167a5c37/src/main/scala/firrtl_interpreter/FirrtlTerp.scala#L202). How can this be silenced? It's quite a bit of output to see during a test!