"exception Expression key dcache.wen already in stack" when loading riscv-mini's Tile.fir

[taomiao]

firrtl>> load ../riscv-mini/generated-src/Tile.fir
Total FIRRTL Compile Time: 374.3 ms
End of dependency graph
Circuit state created
Exception during evaluation: Expression key dcache._GEN_3 already in stack
Expression Evaluation stack
0 dcache.dataMem_1_3._T_319.en -> dcache._GEN_3
1 dcache._GEN_3:Node -> mux(dcache.ren, UInt<1>("h1"), UInt<1>("h0"))
2 dcache.ren:Node -> and(dcache._T_287, dcache.io_cpu_req_valid)
3 dcache._T_287:Node -> and(dcache.wen, dcache._T_286)
4 dcache.wen:Node -> or(dcache._T_285, dcache.is_alloc)
5 dcache._T_285:Node -> and(dcache._T_282, dcache._T_284)
6 dcache._T_282:Node -> and(dcache.is_write, dcache._T_281)
7 dcache._T_281:Node -> or(dcache.hit, dcache.is_alloc_reg)
8 dcache.hit:Node -> dcache._T_389
9 dcache._T_389:Node -> and(dcache._T_387, dcache._T_388)
10 dcache._T_388:Node -> eq(dcache.metaMem_tag.rmeta.data, dcache.tag_reg)
11 dcache.metaMem_tag.rmeta.en -> dcache._GEN_3
12 dcache._GEN_3:Node -> mux(dcache.ren, UInt<1>("h1"), UInt<1>("h0"))
Error: InterpreterExecption(Expression key dcache._GEN_3 already in stack during warmup evaluation
loaded firrtl file ../riscv-mini/generated-src/Tile.fir
Flags: allow-cycles: false ordered-exec: false

[chick]

This is because the interpreter engine has detected a combinational loop.
The interpreter and the repl have a flag --fr-allow-cycles which will still give you this exception on load but will allow step operations on the circuit anyway.
You should probably create an issue in riscv-mini asking about why the Tile.fir has an apparent loop.