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LiteX based M2 SDR/RF FPGA board.

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                              LiteX based M2 SDR FPGA board.
                           Copyright (c) 2024-2026 Enjoy-Digital.

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LiteX-M2SDR is an open-source SDR board in the M.2 2280 Key M form factor, pairing an ADI AD9361 RFIC (2T2R, 70 MHz – 6 GHz) with a Xilinx Artix-7 XC7A200T FPGA. Gateware, drivers, C API and tools are all open, built on the LiteX framework. Pop it in an M.2 slot, connect antennas, and stream or record I/Q in about 5 minutes with our tools or any SoapySDR-compatible software.

LiteX M2 SDR annotated

Highlights

Contents

  1. Why Another AD936x SDR?
  2. Hardware & Availability
  3. Capabilities
  4. Quick Start
  5. Architecture
  6. Documentation
  7. Contact

Why Another AD936x SDR?

We know what you'll first ask when discovering this project: what's the RFIC? πŸ€” Yes β€” another AD936x-based SDR! πŸ˜„

We've been designing FPGA-based projects for clients with this chip for almost 10 years and still think it has capabilities that haven't been fully tapped by open-source projects. Paired with the LiteX framework, it makes for a minimalist, flexible SDR: a compact M.2 board with a minimal on-board RF frontend that can be specialized externally, a large FPGA, and SerDes lanes that can be used for PCIe, Ethernet, SATA or inter-board links (LiteICLink), down to coherent multi-board MIMO setups on a PCIe M.2 carrier. πŸš€

Yes, this project is also a showcase for LiteX capabilities πŸ˜… β€” rest assured, we'll do our best to gather and implement your requests to make this SDR as flexible and versatile as possible, and to keep a welcoming, friendly community. πŸ€—

This board is proudly developed in France πŸ‡«πŸ‡· by Enjoy-Digital, managing the project and gateware/software development, and our partner Lambdaconcept designing the hardware. πŸ₯–πŸ·

Hardware & Availability

The LiteX-M2SDR board is sold through the Enjoy-Digital Shop. It has been tested with several SoapySDR-compatible applications as well as with our own C utilities.

Note

Availability. The project has been a great success, with more than 500 boards already shipped to happy users! πŸŽ‰ Demand is strong and the current stock is sold out: with AD9361 and XC7A200T component prices rising, we are working with our hardware partner on the next production batch at the current price, and we're confident it will be available again soon. πŸš€

Need a board sooner? We're taking pre-orders at a slightly higher price and launch a small production batch as soon as enough orders are collected (e.g. 50+ boards). Contact us to discuss your requirements!

The board is offered in the M.2 2280 Key M form factor with the SI5351C clock generator, providing flexible clocking from the local XO or an external 10 MHz reference (uFL or FPGA-generated). More details

Note: The SI5351C variant now also covers the features of the former SI5351B variant (FPGA-regulated clocking for software-controlled loops) and advantageously replaces it. Existing SI5351B boards remain supported by the gateware and software.

The same board scales from a single PC to a distributed setup:

Four LiteX-M2SDR boards on an ASUS Hyper M.2 card LiteX-M2SDR on the Acorn Baseboard Mini over Ethernet with PoE
8T8R in a single PC. Four boards on an ASUS Hyper M.2 card with PCIe bifurcation, each streaming over its own PCIe link. Distributed over Ethernet. On the LiteX Acorn Baseboard Mini, the board gets 1G/2.5G (+ experimental 5G) Ethernet (SFP), PoE, PTP time sync and SATA recording. See Ethernet.

Pinout, I/O voltages, PPS input and LED behavior: see the Hardware Reference.

Capabilities

What is available depending on where the board is mounted, and the ./litex_m2sdr.py option that enables it ("β€”" = not available in that setup).

RF & streaming

Feature M.2 slot Acorn Baseboard Mini Build option
2T2R TX/RX, 12-bit, up to 61.44 MSPS βœ… βœ… always included
2T2R at 122.88 MSPS (wide bandwidth) βœ… ΒΉ β€” --with-rfic-oversampling
PCIe streaming βœ… Gen2 x1/x2/x4 βœ… Gen2 x1 --with-pcie --pcie-lanes=1|2|4
Ethernet streaming, 1G/2.5G/experimental 5G (details) β€” βœ… `--with-eth [--eth-phy=2500basex
Hardware timed TX βœ… βœ… always included
libm2sdr C API, utilities, SoapySDR βœ… βœ… host software

Timing & sync

Feature M.2 slot Acorn Baseboard Mini Build option
External 10 MHz reference βœ… Β² βœ… Β² runtime (--sync / clock_source)
PCIe PTM host time sync βœ… Β³ βœ… Β³ --with-pcie-ptm
Ethernet PTP time discipline β€” βœ… --with-eth --with-eth-ptp
PTP-disciplined RFIC reference β€” βœ… Β² --with-eth-ptp-rfic-clock
White Rabbit β€” βœ… --with-white-rabbit

Storage & system

Feature M.2 slot Acorn Baseboard Mini Build option
SATA record/replay β€” βœ… --with-sata
Multiboot / remote update βœ… βœ… always included
GPIO βœ… βœ… --with-gpio

ΒΉ Needs PCIe Gen2 x2/x4 bandwidth. Β² SI5351C variant. Β³ PCIe Gen2 x1 only.

See Building And Loading The Gateware for build details. Prebuilt images for the common configurations are published on the Releases page and can be flashed with scripts/flash_release.py.

Quick Start

On a fresh Ubuntu system, with the board in an M.2 slot and antennas connected:

  1. Install the prerequisites:

    sudo apt install build-essential cmake git \
      pkg-config libsdl2-dev libgl1-mesa-dev \
      libsoapysdr-dev soapysdr-tools libsoapysdr0.8 \
      gnuradio gnuradio-dev libgnuradio-soapy3.10.9t64 gqrx-sdr \
      libsndfile1-dev libsamplerate0-dev
  2. Clone, build and install the kernel driver, utilities, libm2sdr and SoapySDR module:

    git clone https://github.com/enjoy-digital/litex_m2sdr
    cd litex_m2sdr/litex_m2sdr/software
    sudo ./build.py
    sudo modprobe m2sdr   # or reboot
  3. Check the board is detected:

    cd user
    ./m2sdr_util info
    SoapySDRUtil --probe="driver=LiteXM2SDR"
  4. Launch your SDR software (GQRX, GNU Radio, ...) and select the LiteX-M2SDR device through SoapySDR. πŸ“‘

Tip

No I/Q samples in your SDR application? Make sure the m2sdr.ko kernel module matches this source tree (older builds needed IOMMU passthrough, iommu=pt on x86). Overflows/underflows at high sample rates? Switch the CPU governor to performance. Details in Host Setup.

More: build options and manual install Β· Raspberry Pi 5 Β· Orange Pi 5 Max Β· Jetson Orin Β· Ethernet setup Β· C API.

Architecture

PCIe SoC

The PCIe design is the default: no baseboard required. Most of the complexity is handled by LiteX and LitePCIe; the SoC itself exposes an MMAP interface and DMA streams, and integrates the SDR/RFIC cores. LitePCIe and its Linux driver have been battle-tested on several commercial projects. The design is validated at 2T2R @ 61.44 MSPS and handles 2T2R @ 122.88 MSPS oversampling (7.9 Gbps on the PCIe bus). Debug is available over PCIe or JTAG (MMAP peek & poke, LiteScope).

Ethernet SoC

On the Acorn Baseboard Mini, the M.2 SerDes lanes can be used for Ethernet instead of PCIe: LiteEth provides the 1000BASE-X/2500BASE-X PHY, the UDP/IP hardware stack and the streaming/Etherbone front-ends, for control and RX/TX sample streaming bounded by the link bandwidth. See Ethernet.

Documentation

The full index is in doc/README.md.

Getting started Using the board Features Timing & sync Development
Building the software User utilities Ethernet PCIe PTM Building the gateware
Host setup SoapySDR driver SATA Ethernet PTP Debugging guide
Flashing releases GNU Radio Wide bandwidth White Rabbit Hardware reference
Platform guides libm2sdr C API Low latency Changelog
Kernel driver Timed TX

Contact

Got a unique idea or need a tweak? Whether it's custom FPGA/software development or hardware adjustments (like adapter boards) for your LiteX-M2SDR, we're here to help! Feel free to drop us a line or visit our website. We'd love to hear from you!

E-mail: florent@enjoy-digital.fr Website: http://enjoy-digital.fr/

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LiteX based M2 SDR/RF FPGA board.

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