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docs: move the generator details to doc/gen.md (and land #46/#48 on master) - #51

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enjoy-digital merged 6 commits into
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Oct 19, 2026
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enjoy-digital merged 6 commits into
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Two things, on purpose in one PR because the second depends on the first:

  1. docs/ci: README refresh (ECP5, generator section, wishlist), Python 3.9/3.12 CI matrix #46 (docs/ci) and phy: add debounced link_up/connect/disconnect events #48 (link events) never reached master. They were merged while their base branch gen/dma-core still existed, so GitHub merged them into that branch instead of retargeting them to master after gen: fix native sink_data, add data_width/gt_type keys, Vivado for 7-series, control/DMA flavour #45 landed. git merge-base --is-ancestor origin/gen/dma-core origin/master is false, master has neither the link monitor nor the CI matrix. The first commit here is a plain --no-ff merge of gen/dma-core into master (clean, no conflicts), which brings both in unchanged.

  2. Generator documentation moved out of the README. The README keeps a short "Standalone core generation" section (one-line description, the litesata_gen command, a link); the flavours, YAML key table, PHY-name to transceiver mapping and the DMA clock rule move to the new doc/gen.md. Same split as liteeth#291.

Diff against master: README, doc/gen.md, CI workflow, setup.py, litesata/phy/{ctrl.py,__init__.py}, litesata/gen.py, test/test_gen.py, test/test_phy_ctrl.py. Everything but the README/doc split is the already-reviewed content of #46 and #48.

The gen/dma-core branch can be deleted once this is merged.

🤖 Generated with Claude Code

enjoy-digital and others added 6 commits October 19, 2026 14:10
….9/3.12 CI matrix

- README: list the Lattice ECP5 PHY, document the standalone generator (command,
  outputs, YAML keys, PHY names, flavours, clock rule), and refresh the wishlist
  (Lattice PHY support exists; rate negotiation, FLUSH/TRIM/4Kn and AXI-Stream
  ports are the open items).
- CI: run the suite on Python 3.9 and 3.12 (fail-fast off); setup.py now
  requires Python >= 3.9, matching what CI covers.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
Software could only poll the PHY ready bit, and the LiteX IRQ for SATA has
no connect/disconnect source (issue #21). Add LiteSATAPHYLinkMonitor: link_up
rises with ready (which already carries the controller's 5 ms stability time)
and falls only once ready has stayed low for link_down_timeout (100 ms by
default), so the controller's own re-initializations on misalignment or idle
do not generate events while a device unplug does. connect/disconnect are
single-cycle pulses, directly usable as EventSourcePulse triggers.

- LiteSATAPHY: link_down_timeout kwarg (appended), link_up / connect_irq /
  disconnect_irq attributes, link_up field appended to the status CSR.
- gen: link_up, connect and disconnect output pads on both flavours.
- tests: link monitor behaviour (short drop ignored, long drop reported) and
  the generator pads.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
phy: add debounced link_up/connect/disconnect events
docs/ci: README refresh (ECP5, generator section, wishlist), Python 3.9/3.12 CI matrix
The README keeps a short section (one-line description, command, link); the flavours, YAML key
table, PHY-name to transceiver mapping and clock rule move to doc/gen.md.

Co-Authored-By: Claude Fable 5.1 <noreply@anthropic.com>
@enjoy-digital

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Full suite on this branch (master + gen/dma-core merge + doc split): python3 -m pytest -q → 34 passed, 21 subtests passed in 726 s.

@enjoy-digital
enjoy-digital merged commit 5a05f69 into master Oct 19, 2026
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