Issues

• DDR4 Calibration Succeeds But Memtest Hangs Without Printf Statements

  answered-waiting-feedbackbug?question
  enjoy-digital/litedram#369 · Filter by author MojoJojo opened on Oct 3, 2025
  1

• separate DDR and CPU clocks

  enhancementquestion
  enjoy-digital/litedram#363 · Filter by author juanschroeder opened on May 4, 2025
  4

• Wishbone port does not accept more than one operation despite cmd_buffer_depth non-null in LiteDram yaml file,

  answered-waiting-feedbackbug?
  enjoy-digital/litedram#355 · Filter by author fontamsoc opened on Mar 30, 2024
  2

• litedram with vexriscv DDR4 SODIMM fails memtest (Xilinx VU9P + spd)

  bug?question
  enjoy-digital/litedram#349 · Filter by author jersey99 opened on Oct 5, 2023
  8

• Underclocking DRAM controler to increase access time

  question
  enjoy-digital/litedram#346 · Filter by author denishoornaert opened on Aug 27, 2023

• Axi port write data error

  answered-waiting-feedbackbug?
  enjoy-digital/litedram#342 · Filter by author Yuxin-Yu opened on Jun 7, 2023
  9

• DDR4 reads without DQS at high speeds?

  question
  enjoy-digital/litedram#328 · Filter by author alexey-morozov opened on Feb 28, 2023
  2

• LiteDRAM USPDDRPHY unable to meet DDR4 timing requirements?

  bug?question
  enjoy-digital/litedram#303 · Filter by author jaccharrison opened on Mar 28, 2022
  9

• Why is my simulation different to my target in regard to "address endianness"?

  question
  enjoy-digital/litedram#251 · Filter by author nickoe opened on May 9, 2021
  1

• LPDDR4 / Add optional features support

  enhancementhelp-wanted
  enjoy-digital/litedram#239 · Filter by author jedrzejboczar opened on Mar 31, 2021

• Add support for DDR3 in MAX10

  help-wantednew-feature
  enjoy-digital/litedram#233 · Filter by author rdolbeau opened on Feb 15, 2021
  5

• Wrong DQS pattern preamble/postamble

  bug?question
  enjoy-digital/litedram#225 · Filter by author jedrzejboczar opened on Dec 10, 2020
  3

• Core Question

  add-answer-to-wikiquestion
  enjoy-digital/litedram#219 · Filter by author vasimr opened on Oct 2, 2020
  4

• Feedback / Contribution / Support

  guide
  enjoy-digital/litedram#214 · Filter by author enjoy-digital opened on Aug 3, 2020

• Add support for Etron RPC DRAM

  new-feature
  enjoy-digital/litedram#211 · Filter by author jedrzejboczar opened on Jul 28, 2020
  7

• Improve crossbar's interface to avoid bottleneck when accessing different banks from the same port.

  enhancement
  enjoy-digital/litedram#209 · Filter by author enjoy-digital opened on Jul 24, 2020
  1

• ECP5: Use ODDRX1F for address and command bus

  enhancement
  enjoy-digital/litedram#194 · Filter by author kingoflolz opened on May 15, 2020
  8

• Move tRRD to SpeedgradeTimings?

  enhancementneeds-review
  enjoy-digital/litedram#185 · Filter by author enjoy-digital opened on Apr 25, 2020

• Inconsistencies between SPD data and datasheets.

  needs-review
  enjoy-digital/litedram#184 · Filter by author enjoy-digital opened on Apr 25, 2020
  2

• Refresh S6DDRPHY

  enhancementhelp-wanted
  enjoy-digital/litedram#182 · Filter by author enjoy-digital opened on Apr 23, 2020
  14

• Use consistent addressing in BIST/Pattern generators

  enhancement
  enjoy-digital/litedram#164 · Filter by author jedrzejboczar opened on Mar 13, 2020

• Benchmark: Allow testing complex/pre-defined access patterns

  enhancement
  enjoy-digital/litedram#113 · Filter by author enjoy-digital opened on Jan 28, 2020

• Allow sharing bank machines between banks

  enhancementhelp-wanted
  enjoy-digital/litedram#75 · Filter by author enjoy-digital opened on Feb 13, 2019

• DDR4 / Add optional features support

  help-wantednew-feature
  enjoy-digital/litedram#63 · Filter by author enjoy-digital opened on Nov 9, 2018

• Multirank: add dynamic ODT

  enhancementhelp-wanted
  enjoy-digital/litedram#39 · Filter by author enjoy-digital opened on Sep 10, 2018