An Implementation of a multi-channel logic analyzer. It will support features from the already produced GUI from sump.org to record data, change trigger events, and send recorded data out on a RS232 Tx/Rx communication path.
Project Goals:
- Using VHDL, develop a generic model of a logic analyzer that will require minimal modifications to target different FPGA vendors and their associated technologies
- Provide a means of downloading captured data to a computer
- Develop testbenches for functional validation of design at each hierarchical level
- Develop a simple device-under-test model for exercising and demonstrating the system capabilities
- Demonstrate design implementation on FPGA development board, which is to be determined