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Sarthak7651/README.md

Hi, I'm Sarthak Pandey 👋

RTL Design & Verification Engineer | VLSI | Digital Design

I build and verify digital hardware using Verilog/SystemVerilog, with a focus on RTL design, digital systems, communication protocols, and Design Verification.

Currently strengthening my skills in RTL Design, SystemVerilog, UVM, Functional Verification, FPGA/ASIC design flow, and semiconductor technologies.

🛠️ Technical Skills

HDL / Verification

  • Verilog HDL
  • SystemVerilog
  • UVM
  • Functional Verification
  • Testbench Development
  • Assertions & Coverage

Digital / RTL Design

  • Combinational & Sequential Logic
  • FSM Design
  • Counters & Registers
  • Clock Dividers
  • CDC & Synchronization
  • SPI Protocol
  • BIST Architecture
  • LFSR & MISR
  • RTL Synthesis

Tools

  • Xilinx Vivado
  • Yosys
  • Verilator
  • Icarus Verilog
  • GTKWave
  • Graphviz
  • VS Code
  • Git & GitHub

Programming

  • C
  • Python

🚀 Featured Projects

🔹 SPI Protocol with Built-In Self-Test (BIST)

A synthesizable Verilog implementation of an SPI Master/Slave system with integrated BIST.

Highlights

  • SPI Master & Slave architecture
  • Configurable SPI operation
  • BIST controller with FSM
  • LFSR-based pseudo-random pattern generation
  • MISR-based signature analysis
  • Fixed-pattern and walking-1 testing
  • Loopback-based self-test architecture
  • Synthesizable RTL

Focus: RTL Design • SPI • BIST • LFSR • MISR • FSM • Verification

🔹 CDAC Verilog HDL Collection

A structured collection of RTL designs and simulation exercises developed during C-DAC training.

Includes:

  • Combinational logic
  • Sequential circuits
  • Registers
  • Counters
  • Multiplexers
  • FSMs
  • Testbenches
  • RTL design exercises

Focus: Verilog • RTL Design • Digital Logic • FSM • Simulation

🔹 Verilog Practice

Hands-on Verilog implementations covering fundamental RTL coding concepts and hardware modeling techniques.

Focus: Verilog • RTL Coding • Digital Design

📚 Currently Learning

  • Advanced SystemVerilog
  • UVM
  • RTL Design Methodology
  • Design Verification
  • CDC & Reset Design
  • ASIC Design Flow
  • FPGA Design Flow
  • Low-Power Design
  • Semiconductor / VLSI Design

🎯 Career Interests

I'm interested in opportunities related to:

RTL Design | Design Verification | FPGA | ASIC | VLSI | SoC

I'm particularly interested in building reliable, synthesizable RTL and developing robust verification environments for digital systems.

📊 GitHub Activity

GitHub Stats

🤝 Connect With Me

LinkedIn

GitHub

⭐ Feel free to explore my repositories and connect with me for VLSI, RTL Design, and Design Verification opportunities.

Popular repositories Loading

  1. HDL_BITS_SOLUTION HDL_BITS_SOLUTION Public

    A collection of Verilog HDL solutions to HDLBits problems, covering combinational and sequential logic, multiplexers, registers, counters, FSMs, arithmetic circuits, memory, and more. This reposito…

    Verilog 1

  2. CDAC_VERILOG_HDL CDAC_VERILOG_HDL Public

    A comprehensive collection of Verilog HDL designs, simulation testbenches, and hardware description projects developed during the C-DAC training program. Covers concepts from basic combinational lo…

    Verilog

  3. SPI-Bus-Protocol-with-Built-In-Self-Test-BIST- SPI-Bus-Protocol-with-Built-In-Self-Test-BIST- Public

    A Verilog implementation of the SPI (Serial Peripheral Interface) protocol with an integrated Built-In Self-Test (BIST) module. The project features synthesizable SPI Master/Slave designs, automati…

    Verilog

  4. Sarthak7651 Sarthak7651 Public

    RTL Design & Verification Engineer | Verilog • SystemVerilog • UVM • Digital Design | VLSI & SoC

  5. ANALOG_LAYOUT ANALOG_LAYOUT Public

    Scheme

  6. Electronic_bit_Solution Electronic_bit_Solution Public

    Verilog