M.S. student @ ICT, CAS | Design Verification | Computer Architecture | FPGA
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Institute of Computing Technology, Chinese Academy of Sciences (ICT, CAS)
- Beijing, China
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07:24
(UTC +08:00) - in/zijian-jiang-896765393
Highlights
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Pinned Loading
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hpdcache-uvm
hpdcache-uvm PublicUVM verification environment for OpenHW Core-V HPDcache
SystemVerilog 3
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cv-hpdcache
cv-hpdcache PublicForked from openhwfoundation/cv-hpdcache
RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
SystemVerilog
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core-v-verif
core-v-verif PublicForked from openhwfoundation/core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
Assembly
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