Skip to content
View Arunachalam-212223060022's full-sized avatar
🎯
Focusing
🎯
Focusing

Block or report Arunachalam-212223060022

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Content in all repositories owned by your account will be closed.
Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

🔥 About Me

I’m Arunachalam, an Electronics and Communication Engineering student with a focused interest in VLSI ⚙️, RTL design 🧩, FPGA development ⚡, and embedded systems 🔧. I’m driven by a genuine curiosity to understand how hardware behaves beyond abstractions—how signals propagate, how timing constraints shape design, and how a system evolves from a conceptual block diagram into a functioning implementation.

My learning process is centered around a structured engineering cycle: simulate → observe → debug → refine → build. I enjoy examining digital systems from both functional and timing perspectives, using HDL-based design to express hardware behavior with clarity and precision.

I’m currently strengthening my foundation in digital logic, RTL architecture, synthesis workflows, timing analysis, and system-level design. Whether I’m refining an RTL module, troubleshooting a waveform, or developing an embedded application, I aim to create solutions that are technically sound, efficient, and thoughtfully engineered.


🧾 Terminal Card

Who am I: Arunachalam – ECE | VLSI | RTL | Embedded Systems

focus--areas: RTL Design | FPGA | Embedded Systems | Digital Logic | Simulation

mindset: iterate → simulate → debug → refine → build


⚡ FUN FACT

Blue LEDs were considered "impossible" for over 30 years.
Their invention in 1993 made white LEDs, RGB screens,
and almost all modern displays possible.

🧠 Skill Radar

🚀 Tech Stack

💻 Programming & HDL

C • C++ • Python • Embedded C • Verilog • RTL

📡 Electronics & Embedded

ESP-32 • Arduino • IoT • Sensors • Actuators • Digital/Analog Electronics

🔧 VLSI / EDA Tools

Quartus • Vivado • Cadence Virtuoso • LTspice • Multisim • Proteus • PCB Layout

🧪 Testing & Simulation

Timing Analysis • Logic Analysis • Testbench Creation • RTL Synthesis • Hardware Debug

🛠 Platforms

VS Code • Git • Google Colab • MATLAB • TinkerCAD • Arduino IDE


🧪 Projects

🔹 Indoor Navigation using A* Algorithm

Grid-based routing with A* and simulated pathfinding.

🔹 Smart Pill Dispenser (ESP32)

Scheduled medication dispenser using ESP32, sensors and embedded logic.

🔹 Traffic Light Controller (FPGA + Verilog)

FSM-based controller designed in Verilog and synthesized using Quartus.


Hey snake... stopppp eating my contributions 😭!!!


💼 Experience

NSIC Technical Services Centre — Intern
Circuit design, simulation and hardware testing.

Codec Technology — VLSI Intern
Verilog, RTL, FPGA workflows, debugging & synthesis.

Freelance Teaching — 2023–Present
STEM tutoring with a concept-first approach.


🎓 Education

  • B.E. Electronics & Communication Engineering — CGPA: 8.4
    Saveetha Engineering College, Chennai

  • Higher Secondary (XII) — 81%
    DAV MHSS, Chennai


🌐 Let’s Connect

✨ Thanks for scrolling — you're awesome.

Pinned Loading

  1. rtl_edge_analytic_SEAP1 rtl_edge_analytic_SEAP1 Public

    🚀 A high-speed FPGA-based streaming analytics engine (SEAP-1) for real-time edge intelligence, combining a fully pipelined architecture with low-latency ⚡ and high-throughput processing for fast, e…

    Verilog 1 2

  2. CNN-Accelerator CNN-Accelerator Public

    Hardware-accelerated CNN on Xilinx Zynq-7020 FPGA for real-time Person/Object detection. Built with Vitis HLS, Vivado & PYNQ — no Vitis AI, no FINN.

    Verilog 8 2

  3. traffic_light_controller_fpga traffic_light_controller_fpga Public

    🚦 Smart Traffic Light Controller built on FPGA using Verilog HDL. Implements Red–Yellow–Green light sequencing with an emergency vehicle priority system. Fully simulated in Xilinx Vivado — clean lo…

    1 1

  4. riscv_soc riscv_soc Public

    A custom RISC-V System-on-Chip (SoC) designed in Verilog HDL, featuring processor core integration, memory subsystems, UART communication, GPIO peripherals, and FPGA-ready implementation. The proje…

    Verilog 3 1