Skip to content

Commit e7567e8

Browse files
yans6666yans6666
committed
[bsp][stm32] Add stm32n657-st-nucleo BSP
1 parent e538ad7 commit e7567e8

84 files changed

Lines changed: 15340 additions & 20 deletions

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

‎.github/ALL_BSP_COMPILE.json‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -221,6 +221,7 @@
221221
"stm32/stm32h7r7-artpi2",
222222
"stm32/stm32mp157a-st-discovery",
223223
"stm32/stm32mp157a-st-ev1",
224+
"stm32/stm32n657-st-nucleo",
224225
"stm32/stm32u575-st-nucleo",
225226
"stm32/stm32u585-iot02a",
226227
"stm32/stm32wb55-st-nucleo"

‎bsp/README.md‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -157,6 +157,7 @@ This document is based on the RT-Thread mainline repository and categorizes the
157157
| [stm32l552-st-nucleo](stm32/stm32l552-st-nucleo) | ✅ | ✅ | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
158158
| [stm32mp157a-st-discovery](stm32/stm32mp157a-st-discovery) | ✅ | ✅ | ✅ | - | ✅ | - | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | ✅ | - | - | - | - | - | - | - | - | ✅ | - | - | - |
159159
| [stm32mp157a-st-ev1](stm32/stm32mp157a-st-ev1) | ✅ | ✅ | ✅ | ✅ | ✅ | - | ✅ | ✅ | ✅ | ✅ | - | ✅ | - | - | ✅ | - | ✅ | - | - | - | ✅ | - | ✅ | ✅ | - | - | - |
160+
| [stm32n657-st-nucleo](stm32/stm32n657-st-nucleo) | ✅ | ✅ | - | - | - | - | - | ✅ | - | ✅ | - | ✅ | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
160161
| [stm32u575-st-nucleo](stm32/stm32u575-st-nucleo) | ✅ | ✅ | ✅ | - | - | - | - | - | ✅ | ✅ | - | ✅ | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
161162
| [stm32u585-iot02a](stm32/stm32u585-iot02a) | ✅ | ✅ | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
162163
| [stm32wb55-st-nucleo](stm32/stm32wb55-st-nucleo) | ✅ | ✅ | ✅ | - | - | - | - | ✅ | ✅ | - | ✅ | ✅ | - | ✅ | - | - | - | - | - | - | - | - | - | - | - | - | - |

‎bsp/stm32/README.md‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -99,6 +99,8 @@ STM32 系列 BSP 目前支持情况如下表所示：
9999
| **MP1 系列** | |
100100
| [stm32mp157a-st-discovery](stm32mp157a-st-discovery) | ST 官方 STM32MP157A-DK1 开发板 |
101101
| [stm32mp157a-st-ev1](stm32mp157a-st-ev1) | ST 官方 STM32MP157A-EV1 开发板 |
102+
| **N6 系列** | |
103+
| [stm32n657-st-nucleo](stm32n657-st-nucleo) | ST 官方 STM32N657-Nucleo 开发板 |
102104
| **WB 系列** | |
103105
| [stm32wb55-st-nucleo](stm32wb55-st-nucleo) | ST 官方 STM32WB55-Nucleo 开发板 |
104106
| [stm32wl55-st-nucleo](stm32wl55-st-nucleo) | ST 官方 STM32WL55-Nucleo 开发板 |

‎bsp/stm32/libraries/HAL_Drivers/drivers/config/n6/adc_config.h‎

Lines changed: 93 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,93 @@
1+
/*
2+
* Copyright (c) 2006-2023, RT-Thread Development Team
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*
6+
* Change Logs:
7+
* Date Author Notes
8+
* 2018-12-06 zylx first version
9+
*/
10+
11+
#ifndef __ADC_CONFIG_H__
12+
#define __ADC_CONFIG_H__
13+
14+
#include <rtthread.h>
15+
16+
#ifdef __cplusplus
17+
extern "C" {
18+
#endif
19+
20+
#ifdef BSP_USING_ADC1
21+
#ifndef ADC1_CONFIG
22+
#define ADC1_CONFIG \
23+
{ \
24+
.Instance = ADC1, \
25+
.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4, \
26+
.Init.Resolution = ADC_RESOLUTION_16B, \
27+
.Init.ScanConvMode = ADC_SCAN_DISABLE, \
28+
.Init.EOCSelection = ADC_EOC_SINGLE_CONV, \
29+
.Init.LowPowerAutoWait = DISABLE, \
30+
.Init.ContinuousConvMode = DISABLE, \
31+
.Init.NbrOfConversion = 1, \
32+
.Init.DiscontinuousConvMode = DISABLE, \
33+
.Init.NbrOfDiscConversion = 1, \
34+
.Init.ExternalTrigConv = ADC_SOFTWARE_START, \
35+
.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE, \
36+
.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR, \
37+
.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN, \
38+
.Init.OversamplingMode = DISABLE, \
39+
}
40+
#endif /* ADC1_CONFIG */
41+
#endif /* BSP_USING_ADC1 */
42+
43+
#ifdef BSP_USING_ADC2
44+
#ifndef ADC2_CONFIG
45+
#define ADC2_CONFIG \
46+
{ \
47+
.Instance = ADC2, \
48+
.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4, \
49+
.Init.Resolution = ADC_RESOLUTION_16B, \
50+
.Init.ScanConvMode = ADC_SCAN_DISABLE, \
51+
.Init.EOCSelection = ADC_EOC_SINGLE_CONV, \
52+
.Init.LowPowerAutoWait = DISABLE, \
53+
.Init.ContinuousConvMode = DISABLE, \
54+
.Init.NbrOfConversion = 1, \
55+
.Init.DiscontinuousConvMode = DISABLE, \
56+
.Init.NbrOfDiscConversion = 1, \
57+
.Init.ExternalTrigConv = ADC_SOFTWARE_START, \
58+
.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE, \
59+
.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR, \
60+
.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN, \
61+
.Init.OversamplingMode = DISABLE, \
62+
}
63+
#endif /* ADC2_CONFIG */
64+
#endif /* BSP_USING_ADC2 */
65+
66+
#ifdef BSP_USING_ADC3
67+
#ifndef ADC3_CONFIG
68+
#define ADC3_CONFIG \
69+
{ \
70+
.Instance = ADC3, \
71+
.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4, \
72+
.Init.Resolution = ADC_RESOLUTION_16B, \
73+
.Init.ScanConvMode = ADC_SCAN_DISABLE, \
74+
.Init.EOCSelection = ADC_EOC_SINGLE_CONV, \
75+
.Init.LowPowerAutoWait = DISABLE, \
76+
.Init.ContinuousConvMode = DISABLE, \
77+
.Init.NbrOfConversion = 1, \
78+
.Init.DiscontinuousConvMode = DISABLE, \
79+
.Init.NbrOfDiscConversion = 1, \
80+
.Init.ExternalTrigConv = ADC_SOFTWARE_START, \
81+
.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE, \
82+
.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR, \
83+
.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN, \
84+
.Init.OversamplingMode = DISABLE, \
85+
}
86+
#endif /* ADC3_CONFIG */
87+
#endif /* BSP_USING_ADC3 */
88+
89+
#ifdef __cplusplus
90+
}
91+
#endif
92+
93+
#endif /* __ADC_CONFIG_H__ */

‎bsp/stm32/libraries/HAL_Drivers/drivers/config/n6/dac_config.h‎

Lines changed: 42 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,42 @@
1+
/*
2+
* Copyright (c) 2006-2023, RT-Thread Development Team
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*
6+
* Change Logs:
7+
* Date Author Notes
8+
* 2020-06-16 thread-liu first version
9+
*/
10+
11+
#ifndef __DAC_CONFIG_H__
12+
#define __DAC_CONFIG_H__
13+
14+
#include <rtthread.h>
15+
16+
#ifdef __cplusplus
17+
extern "C" {
18+
#endif
19+
20+
#ifdef BSP_USING_DAC1
21+
#ifndef DAC1_CONFIG
22+
#define DAC1_CONFIG \
23+
{ \
24+
.Instance = DAC1, \
25+
}
26+
#endif /* DAC2_CONFIG */
27+
#endif /* BSP_USING_DAC2 */
28+
29+
#ifdef BSP_USING_DAC2
30+
#ifndef DAC2_CONFIG
31+
#define DAC2_CONFIG \
32+
{ \
33+
.Instance = DAC2, \
34+
}
35+
#endif /* DAC2_CONFIG */
36+
#endif /* BSP_USING_DAC2 */
37+
38+
#ifdef __cplusplus
39+
}
40+
#endif
41+
42+
#endif /* __DAC_CONFIG_H__ */

‎bsp/stm32/libraries/HAL_Drivers/drivers/config/n6/dma_config.h‎

Lines changed: 218 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,218 @@
1+
/*
2+
* Copyright (c) 2006-2023, RT-Thread Development Team
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*
6+
* Change Logs:
7+
* Date Author Notes
8+
* 2019-01-02 zylx first version
9+
* 2019-01-08 SummerGift clean up the code
10+
* 2020-05-02 whj4674672 support stm32h7 dma1 and dma2
11+
*/
12+
13+
#ifndef __DMA_CONFIG_H__
14+
#define __DMA_CONFIG_H__
15+
16+
#include <rtthread.h>
17+
18+
#ifdef __cplusplus
19+
extern "C" {
20+
#endif
21+
22+
/* N6 provides one GPDMA1 controller with 16 independent channels. Keep the
23+
* legacy endpoint table below source-compatible while assigning each legacy
24+
* stream a unique GPDMA channel. */
25+
#define DMA1_Stream0 GPDMA1_Channel0
26+
#define DMA1_Stream1 GPDMA1_Channel1
27+
#define DMA1_Stream2 GPDMA1_Channel2
28+
#define DMA1_Stream3 GPDMA1_Channel3
29+
#define DMA1_Stream4 GPDMA1_Channel4
30+
#define DMA1_Stream5 GPDMA1_Channel5
31+
#define DMA1_Stream6 GPDMA1_Channel6
32+
#define DMA1_Stream7 GPDMA1_Channel7
33+
#define DMA2_Stream0 GPDMA1_Channel8
34+
#define DMA2_Stream1 GPDMA1_Channel9
35+
#define DMA2_Stream2 GPDMA1_Channel10
36+
#define DMA2_Stream3 GPDMA1_Channel11
37+
#define DMA2_Stream4 GPDMA1_Channel12
38+
#define DMA2_Stream5 GPDMA1_Channel13
39+
#define DMA2_Stream6 GPDMA1_Channel14
40+
#define DMA2_Stream7 GPDMA1_Channel15
41+
#define DMA1_Stream0_IRQn GPDMA1_Channel0_IRQn
42+
#define DMA1_Stream1_IRQn GPDMA1_Channel1_IRQn
43+
#define DMA1_Stream2_IRQn GPDMA1_Channel2_IRQn
44+
#define DMA1_Stream3_IRQn GPDMA1_Channel3_IRQn
45+
#define DMA1_Stream4_IRQn GPDMA1_Channel4_IRQn
46+
#define DMA1_Stream5_IRQn GPDMA1_Channel5_IRQn
47+
#define DMA1_Stream6_IRQn GPDMA1_Channel6_IRQn
48+
#define DMA1_Stream7_IRQn GPDMA1_Channel7_IRQn
49+
#define DMA2_Stream0_IRQn GPDMA1_Channel8_IRQn
50+
#define DMA2_Stream1_IRQn GPDMA1_Channel9_IRQn
51+
#define DMA2_Stream2_IRQn GPDMA1_Channel10_IRQn
52+
#define DMA2_Stream3_IRQn GPDMA1_Channel11_IRQn
53+
#define DMA2_Stream4_IRQn GPDMA1_Channel12_IRQn
54+
#define DMA2_Stream5_IRQn GPDMA1_Channel13_IRQn
55+
#define DMA2_Stream6_IRQn GPDMA1_Channel14_IRQn
56+
#define DMA2_Stream7_IRQn GPDMA1_Channel15_IRQn
57+
#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_GPDMA1EN
58+
#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_GPDMA1EN
59+
#define SPI1_RX_DMA_REQUEST GPDMA1_REQUEST_SPI1_RX
60+
#define SPI1_TX_DMA_REQUEST GPDMA1_REQUEST_SPI1_TX
61+
#define SPI2_RX_DMA_REQUEST GPDMA1_REQUEST_SPI2_RX
62+
#define SPI2_TX_DMA_REQUEST GPDMA1_REQUEST_SPI2_TX
63+
#define SPI3_RX_DMA_REQUEST GPDMA1_REQUEST_SPI3_RX
64+
#define SPI3_TX_DMA_REQUEST GPDMA1_REQUEST_SPI3_TX
65+
#define SPI4_RX_DMA_REQUEST GPDMA1_REQUEST_SPI4_RX
66+
#define SPI4_TX_DMA_REQUEST GPDMA1_REQUEST_SPI4_TX
67+
#define SPI5_RX_DMA_REQUEST GPDMA1_REQUEST_SPI5_RX
68+
#define SPI5_TX_DMA_REQUEST GPDMA1_REQUEST_SPI5_TX
69+
#define SPI6_RX_DMA_REQUEST GPDMA1_REQUEST_SPI6_RX
70+
#define SPI6_TX_DMA_REQUEST GPDMA1_REQUEST_SPI6_TX
71+
#define DMA_REQUEST_USART2_RX GPDMA1_REQUEST_USART2_RX
72+
#define DMA_REQUEST_USART2_TX GPDMA1_REQUEST_USART2_TX
73+
74+
/* DMA1 stream0 */
75+
#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
76+
#define UART2_DMA_RX_IRQHandler DMA1_Stream0_IRQHandler
77+
#define UART2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
78+
#define UART2_RX_DMA_INSTANCE DMA1_Stream0
79+
#define UART2_RX_DMA_REQUEST DMA_REQUEST_USART2_RX
80+
#define UART2_RX_DMA_IRQ DMA1_Stream0_IRQn
81+
#endif
82+
83+
/* DMA1 stream1 */
84+
#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE)
85+
#define UART2_DMA_TX_IRQHandler DMA1_Stream1_IRQHandler
86+
#define UART2_TX_DMA_RCC RCC_AHB1ENR_DMA1EN
87+
#define UART2_TX_DMA_INSTANCE DMA1_Stream1
88+
#define UART2_TX_DMA_REQUEST DMA_REQUEST_USART2_TX
89+
#define UART2_TX_DMA_IRQ DMA1_Stream1_IRQn
90+
#endif
91+
92+
/* DMA1 stream2 */
93+
#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
94+
#define SPI3_DMA_RX_IRQHandler DMA1_Stream2_IRQHandler
95+
#define SPI3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
96+
#define SPI3_RX_DMA_INSTANCE DMA1_Stream2
97+
#define SPI3_RX_DMA_IRQ DMA1_Stream2_IRQn
98+
#endif
99+
100+
/* DMA1 stream3 */
101+
#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
102+
#define SPI2_DMA_RX_IRQHandler DMA1_Stream3_IRQHandler
103+
#define SPI2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
104+
#define SPI2_RX_DMA_INSTANCE DMA1_Stream3
105+
#define SPI2_RX_DMA_IRQ DMA1_Stream3_IRQn
106+
#endif
107+
108+
/* DMA1 stream4 */
109+
#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
110+
#define SPI2_DMA_TX_IRQHandler DMA1_Stream4_IRQHandler
111+
#define SPI2_TX_DMA_RCC RCC_AHB1ENR_DMA1EN
112+
#define SPI2_TX_DMA_INSTANCE DMA1_Stream4
113+
#define SPI2_TX_DMA_IRQ DMA1_Stream4_IRQn
114+
#endif
115+
116+
117+
/* DMA1 stream5 */
118+
#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
119+
#define SPI3_DMA_TX_IRQHandler DMA1_Stream5_IRQHandler
120+
#define SPI3_TX_DMA_RCC RCC_AHB1ENR_DMA1EN
121+
#define SPI3_TX_DMA_INSTANCE DMA1_Stream5
122+
#define SPI3_TX_DMA_IRQ DMA1_Stream5_IRQn
123+
#endif
124+
125+
/* DMA1 stream6 */
126+
127+
/* DMA1 stream7 */
128+
#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
129+
#define SPI3_DMA_TX_IRQHandler DMA1_Stream7_IRQHandler
130+
#define SPI3_TX_DMA_RCC RCC_AHB1ENR_DMA1EN
131+
#define SPI3_TX_DMA_INSTANCE DMA1_Stream7
132+
#define SPI3_TX_DMA_IRQ DMA1_Stream7_IRQn
133+
#endif
134+
135+
/* DMA1 stream6/7 are available for SPI6 when SPI3 TX uses stream5. */
136+
#if defined(BSP_SPI6_RX_USING_DMA) && !defined(SPI6_RX_DMA_INSTANCE)
137+
#define SPI6_DMA_RX_IRQHandler DMA1_Stream6_IRQHandler
138+
#define SPI6_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
139+
#define SPI6_RX_DMA_INSTANCE DMA1_Stream6
140+
#define SPI6_RX_DMA_IRQ DMA1_Stream6_IRQn
141+
#endif
142+
143+
#if defined(BSP_SPI6_TX_USING_DMA) && !defined(SPI6_TX_DMA_INSTANCE)
144+
#define SPI6_DMA_TX_IRQHandler DMA1_Stream7_IRQHandler
145+
#define SPI6_TX_DMA_RCC RCC_AHB1ENR_DMA1EN
146+
#define SPI6_TX_DMA_INSTANCE DMA1_Stream7
147+
#define SPI6_TX_DMA_IRQ DMA1_Stream7_IRQn
148+
#endif
149+
150+
/* DMA2 stream0 */
151+
#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
152+
#define SPI1_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler
153+
#define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
154+
#define SPI1_RX_DMA_INSTANCE DMA2_Stream0
155+
#define SPI1_RX_DMA_IRQ DMA2_Stream0_IRQn
156+
#endif
157+
158+
/* DMA2 stream1 */
159+
#if defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
160+
#define SPI4_DMA_TX_IRQHandler DMA2_Stream1_IRQHandler
161+
#define SPI4_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
162+
#define SPI4_TX_DMA_INSTANCE DMA2_Stream1
163+
#define SPI4_TX_DMA_IRQ DMA2_Stream1_IRQn
164+
#endif
165+
166+
/* DMA2 stream2 */
167+
#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
168+
#define SPI1_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler
169+
#define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
170+
#define SPI1_RX_DMA_INSTANCE DMA2_Stream2
171+
#define SPI1_RX_DMA_IRQ DMA2_Stream2_IRQn
172+
#endif
173+
174+
/* DMA2 stream3 */
175+
#if defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE)
176+
#define SPI5_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler
177+
#define SPI5_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
178+
#define SPI5_RX_DMA_INSTANCE DMA2_Stream3
179+
#define SPI5_RX_DMA_IRQ DMA2_Stream3_IRQn
180+
#endif
181+
182+
/* DMA2 stream4 */
183+
#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE)
184+
#define SPI5_DMA_TX_IRQHandler DMA2_Stream4_IRQHandler
185+
#define SPI5_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
186+
#define SPI5_TX_DMA_INSTANCE DMA2_Stream4
187+
#define SPI5_TX_DMA_IRQ DMA2_Stream4_IRQn
188+
#endif
189+
190+
/* DMA2 stream5 */
191+
#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
192+
#define SPI1_DMA_TX_IRQHandler DMA2_Stream5_IRQHandler
193+
#define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
194+
#define SPI1_TX_DMA_INSTANCE DMA2_Stream5
195+
#define SPI1_TX_DMA_IRQ DMA2_Stream5_IRQn
196+
#endif
197+
198+
/* DMA2 stream6 */
199+
#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE)
200+
#define SPI5_DMA_TX_IRQHandler DMA2_Stream6_IRQHandler
201+
#define SPI5_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
202+
#define SPI5_TX_DMA_INSTANCE DMA2_Stream6
203+
#define SPI5_TX_DMA_IRQ DMA2_Stream6_IRQn
204+
#endif
205+
206+
/* DMA2 stream7 */
207+
#if defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE)
208+
#define QSPI_DMA_IRQHandler DMA2_Stream7_IRQHandler
209+
#define QSPI_DMA_RCC RCC_AHB1ENR_DMA2EN
210+
#define QSPI_DMA_INSTANCE DMA2_Stream7
211+
#define QSPI_DMA_IRQ DMA2_Stream7_IRQn
212+
#endif
213+
214+
#ifdef __cplusplus
215+
}
216+
#endif
217+
218+
#endif /* __DMA_CONFIG_H__ */

0 commit comments

Comments
 (0)