[libcpu][risc-v] Refactor the RISC-V architecture port

Introduce an opt-in unified RISC-V common layer for RV32 and RV64 while keeping existing BSPs on the legacy implementation during migration.

- use ARCH_RISCV and ARCH_CPU_64BIT for architecture and XLEN selection
- unify context, trap, MMU, cache, timer, SBI, SMP and ISA handling
- add PLIC, CLIC, ACLINT, APLIC and IMSIC support
- map physical hart IDs to contiguous logical CPU IDs
- add T-Head vendor overrides while preserving legacy ports
- migrate qemu-virt64-riscv with RV32 and RV64 support
- update clock_time, MM, LWP, OFW, PCI and Rust integration

Existing BSPs continue using legacy_common or common64 unless they select RT_USING_RISCV_NEW_COMMON.

Signed-off-by: GuEe-GUI <2991707448@qq.com>

Author: GuEe-GUI

.github/workflows/utest_auto_run.yml

@@ -269,6 +269,12 @@ jobs:
       - name: Build BSP
         if: ${{ env.TOOLCHAIN_INSTALLED != '' && success() }}
         run: |
+          # Keep regular RISC-V jobs UP; SMP coverage has its own matrix entry.
+          if [[ "$TEST_BSP_ROOT" == "bsp/qemu-virt64-riscv" && "${{ matrix.platform.SMP_RUN }}" != "smp" ]]; then
+            echo "# CONFIG_RT_USING_SMP is not set" >> $TEST_BSP_ROOT/.config
+            echo "CONFIG_RT_CPUS_NR=1" >> $TEST_BSP_ROOT/.config
+          fi
+
           # Whether plan to run SMP?
           if [[ "${{ matrix.platform.SMP_RUN }}"  == "smp" ]]; then
             cat $UTEST_CONFIG_ROOT/smp/smp.cfg >> $TEST_BSP_ROOT/.config
@@ -338,6 +344,39 @@ jobs:
             $QEMU_BIN -cpu c906fd -M $TEST_QEMU_MACHINE -kernel $TEST_BSP_ROOT/rtthread.bin -nographic \
             -drive if=none,file=$TEST_BSP_ROOT/sd.bin,format=raw,id=blk0 -device virtio-blk-device,drive=blk0,bus=virtio-mmio-bus.0 \
             > qemu_output_$TEST_QEMU_ARCH.log  2>&1 &
+          elif [[ "$TEST_BSP_ROOT" == "bsp/qemu-virt64-riscv" ]]; then
+            cpus=$(grep -E '^#define[[:space:]]+RT_CPUS_NR' "$TEST_BSP_ROOT/rtconfig.h" | awk '{print $3}')
+            cpus=${cpus:-1}
+
+            dtb_args=()
+            if [[ "${{ matrix.platform.KERNEL }}" == "rtsmart" ]]; then
+              # QEMU 6.2 has no satp-mode CPU properties; RT-Smart currently uses an Sv39 VA layout.
+              dtb="$RUNNER_TEMP/qemu-${TEST_QEMU_ARCH}-sv39.dtb"
+              qemu-system-$TEST_QEMU_ARCH \
+                  -M "$TEST_QEMU_MACHINE,dumpdtb=$dtb" \
+                  -cpu rv64 \
+                  -smp "$cpus" \
+                  -m 256M
+              # QEMU 6.2 recreates fw-cfg after loading an external DTB.
+              if fdtget "$dtb" /fw-cfg@10100000 compatible >/dev/null 2>&1; then
+                fdtput -r "$dtb" /fw-cfg@10100000
+              fi
+              for ((cpu = 0; cpu < cpus; cpu++)); do
+                fdtput -t s "$dtb" "/cpus/cpu@$cpu" mmu-type riscv,sv39
+              done
+              dtb_args=(-dtb "$dtb")
+            fi
+
+            qemu-system-$TEST_QEMU_ARCH \
+                -nographic \
+                -M $TEST_QEMU_MACHINE \
+                -cpu rv64 \
+                -smp "$cpus" \
+                -m 256M \
+                -kernel "$TEST_BSP_ROOT/rtthread.bin" \
+                "${dtb_args[@]}" \
+                -append "console=ttyS0 earlycon=sbi" \
+                > qemu_output_$TEST_QEMU_ARCH.log 2>&1 &
           elif [[ "${{ matrix.platform.QEMU_ARCH }}"  == "arm" ]]; then 
             qemu-system-$TEST_QEMU_ARCH \
                 -nographic \