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[bsp][stm32] Add stm32n657-st-nucleo BSP (#11799)
* [bsp][stm32] Add stm32n657-st-nucleo BSP * style: format STM32 HAL drivers and STM32N657 BSP with clang-format
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‎.github/ALL_BSP_COMPILE.json‎

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"stm32/stm32h7r7-artpi2",
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"stm32/stm32mp157a-st-discovery",
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"stm32/stm32mp157a-st-ev1",
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"stm32/stm32n657-st-nucleo",
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"stm32/stm32u575-st-nucleo",
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"stm32/stm32u585-iot02a",
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"stm32/stm32wb55-st-nucleo"

‎bsp/README.md‎

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@@ -157,6 +157,7 @@ This document is based on the RT-Thread mainline repository and categorizes the
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| [stm32l552-st-nucleo](stm32/stm32l552-st-nucleo) | ✅ | ✅ | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
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| [stm32mp157a-st-discovery](stm32/stm32mp157a-st-discovery) | ✅ | ✅ | ✅ | - | ✅ | - | ✅ | ✅ | ✅ | ✅ | ✅ | ✅ | - | - | ✅ | - | - | - | - | - | - | - | - | ✅ | - | - | - |
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| [stm32mp157a-st-ev1](stm32/stm32mp157a-st-ev1) | ✅ | ✅ | ✅ | ✅ | ✅ | - | ✅ | ✅ | ✅ | ✅ | - | ✅ | - | - | ✅ | - | ✅ | - | - | - | ✅ | - | ✅ | ✅ | - | - | - |
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| [stm32n657-st-nucleo](stm32/stm32n657-st-nucleo) | ✅ | ✅ | - | - | - | - | - | ✅ | - | ✅ | - | ✅ | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
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| [stm32u575-st-nucleo](stm32/stm32u575-st-nucleo) | ✅ | ✅ | ✅ | - | - | - | - | - | ✅ | ✅ | - | ✅ | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
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| [stm32u585-iot02a](stm32/stm32u585-iot02a) | ✅ | ✅ | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - | - |
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| [stm32wb55-st-nucleo](stm32/stm32wb55-st-nucleo) | ✅ | ✅ | ✅ | - | - | - | - | ✅ | ✅ | - | ✅ | ✅ | - | ✅ | - | - | - | - | - | - | - | - | - | - | - | - | - |

‎bsp/stm32/README.md‎

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@@ -99,6 +99,8 @@ STM32 系列 BSP 目前支持情况如下表所示：
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| **MP1 系列** | |
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| [stm32mp157a-st-discovery](stm32mp157a-st-discovery) | ST 官方 STM32MP157A-DK1 开发板 |
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| [stm32mp157a-st-ev1](stm32mp157a-st-ev1) | ST 官方 STM32MP157A-EV1 开发板 |
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| **N6 系列** | |
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| [stm32n657-st-nucleo](stm32n657-st-nucleo) | ST 官方 STM32N657-Nucleo 开发板 |
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| **WB 系列** | |
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| [stm32wb55-st-nucleo](stm32wb55-st-nucleo) | ST 官方 STM32WB55-Nucleo 开发板 |
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| [stm32wl55-st-nucleo](stm32wl55-st-nucleo) | ST 官方 STM32WL55-Nucleo 开发板 |

‎bsp/stm32/libraries/HAL_Drivers/drivers/config/n6/adc_config.h‎

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/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018-12-06 zylx first version
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*/
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#ifndef __ADC_CONFIG_H__
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#define __ADC_CONFIG_H__
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#include <rtthread.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef BSP_USING_ADC1
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#ifndef ADC1_CONFIG
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#define ADC1_CONFIG \
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{ \
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.Instance = ADC1, \
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.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4, \
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.Init.Resolution = ADC_RESOLUTION_16B, \
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.Init.ScanConvMode = ADC_SCAN_DISABLE, \
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.Init.EOCSelection = ADC_EOC_SINGLE_CONV, \
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.Init.LowPowerAutoWait = DISABLE, \
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.Init.ContinuousConvMode = DISABLE, \
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.Init.NbrOfConversion = 1, \
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.Init.DiscontinuousConvMode = DISABLE, \
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.Init.NbrOfDiscConversion = 1, \
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.Init.ExternalTrigConv = ADC_SOFTWARE_START, \
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.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE, \
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.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR, \
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.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN, \
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.Init.OversamplingMode = DISABLE, \
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}
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#endif /* ADC1_CONFIG */
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#endif /* BSP_USING_ADC1 */
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#ifdef BSP_USING_ADC2
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#ifndef ADC2_CONFIG
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#define ADC2_CONFIG \
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{ \
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.Instance = ADC2, \
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.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4, \
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.Init.Resolution = ADC_RESOLUTION_16B, \
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.Init.ScanConvMode = ADC_SCAN_DISABLE, \
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.Init.EOCSelection = ADC_EOC_SINGLE_CONV, \
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.Init.LowPowerAutoWait = DISABLE, \
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.Init.ContinuousConvMode = DISABLE, \
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.Init.NbrOfConversion = 1, \
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.Init.DiscontinuousConvMode = DISABLE, \
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.Init.NbrOfDiscConversion = 1, \
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.Init.ExternalTrigConv = ADC_SOFTWARE_START, \
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.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE, \
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.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR, \
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.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN, \
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.Init.OversamplingMode = DISABLE, \
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}
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#endif /* ADC2_CONFIG */
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#endif /* BSP_USING_ADC2 */
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#ifdef BSP_USING_ADC3
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#ifndef ADC3_CONFIG
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#define ADC3_CONFIG \
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{ \
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.Instance = ADC3, \
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.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4, \
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.Init.Resolution = ADC_RESOLUTION_16B, \
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.Init.ScanConvMode = ADC_SCAN_DISABLE, \
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.Init.EOCSelection = ADC_EOC_SINGLE_CONV, \
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.Init.LowPowerAutoWait = DISABLE, \
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.Init.ContinuousConvMode = DISABLE, \
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.Init.NbrOfConversion = 1, \
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.Init.DiscontinuousConvMode = DISABLE, \
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.Init.NbrOfDiscConversion = 1, \
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.Init.ExternalTrigConv = ADC_SOFTWARE_START, \
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.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE, \
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.Init.ConversionDataManagement = ADC_CONVERSIONDATA_DR, \
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.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN, \
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.Init.OversamplingMode = DISABLE, \
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}
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#endif /* ADC3_CONFIG */
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#endif /* BSP_USING_ADC3 */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ADC_CONFIG_H__ */

‎bsp/stm32/libraries/HAL_Drivers/drivers/config/n6/dma_config.h‎

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/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2019-01-02 zylx first version
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* 2019-01-08 SummerGift clean up the code
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* 2020-05-02 whj4674672 support stm32h7 dma1 and dma2
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*/
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#ifndef __DMA_CONFIG_H__
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#define __DMA_CONFIG_H__
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#include <rtthread.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* N6 provides one GPDMA1 controller with 16 independent channels. Keep the
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* legacy endpoint table below source-compatible while assigning each legacy
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* stream a unique GPDMA channel. */
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#define DMA1_Stream0 GPDMA1_Channel0
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#define DMA1_Stream1 GPDMA1_Channel1
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#define DMA1_Stream2 GPDMA1_Channel2
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#define DMA1_Stream3 GPDMA1_Channel3
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#define DMA1_Stream4 GPDMA1_Channel4
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#define DMA1_Stream5 GPDMA1_Channel5
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#define DMA1_Stream6 GPDMA1_Channel6
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#define DMA1_Stream7 GPDMA1_Channel7
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#define DMA2_Stream0 GPDMA1_Channel8
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#define DMA2_Stream1 GPDMA1_Channel9
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#define DMA2_Stream2 GPDMA1_Channel10
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#define DMA2_Stream3 GPDMA1_Channel11
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#define DMA2_Stream4 GPDMA1_Channel12
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#define DMA2_Stream5 GPDMA1_Channel13
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#define DMA2_Stream6 GPDMA1_Channel14
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#define DMA2_Stream7 GPDMA1_Channel15
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#define DMA1_Stream0_IRQn GPDMA1_Channel0_IRQn
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#define DMA1_Stream1_IRQn GPDMA1_Channel1_IRQn
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#define DMA1_Stream2_IRQn GPDMA1_Channel2_IRQn
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#define DMA1_Stream3_IRQn GPDMA1_Channel3_IRQn
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#define DMA1_Stream4_IRQn GPDMA1_Channel4_IRQn
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#define DMA1_Stream5_IRQn GPDMA1_Channel5_IRQn
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#define DMA1_Stream6_IRQn GPDMA1_Channel6_IRQn
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#define DMA1_Stream7_IRQn GPDMA1_Channel7_IRQn
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#define DMA2_Stream0_IRQn GPDMA1_Channel8_IRQn
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#define DMA2_Stream1_IRQn GPDMA1_Channel9_IRQn
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#define DMA2_Stream2_IRQn GPDMA1_Channel10_IRQn
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#define DMA2_Stream3_IRQn GPDMA1_Channel11_IRQn
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#define DMA2_Stream4_IRQn GPDMA1_Channel12_IRQn
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#define DMA2_Stream5_IRQn GPDMA1_Channel13_IRQn
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#define DMA2_Stream6_IRQn GPDMA1_Channel14_IRQn
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#define DMA2_Stream7_IRQn GPDMA1_Channel15_IRQn
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#define DMA1_Stream0_IRQHandler GPDMA1_Channel0_IRQHandler
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#define DMA1_Stream1_IRQHandler GPDMA1_Channel1_IRQHandler
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#define DMA1_Stream2_IRQHandler GPDMA1_Channel2_IRQHandler
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#define DMA1_Stream3_IRQHandler GPDMA1_Channel3_IRQHandler
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#define DMA1_Stream4_IRQHandler GPDMA1_Channel4_IRQHandler
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#define DMA1_Stream5_IRQHandler GPDMA1_Channel5_IRQHandler
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#define DMA1_Stream6_IRQHandler GPDMA1_Channel6_IRQHandler
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#define DMA1_Stream7_IRQHandler GPDMA1_Channel7_IRQHandler
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#define DMA2_Stream0_IRQHandler GPDMA1_Channel8_IRQHandler
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#define DMA2_Stream1_IRQHandler GPDMA1_Channel9_IRQHandler
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#define DMA2_Stream2_IRQHandler GPDMA1_Channel10_IRQHandler
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#define DMA2_Stream3_IRQHandler GPDMA1_Channel11_IRQHandler
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#define DMA2_Stream4_IRQHandler GPDMA1_Channel12_IRQHandler
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#define DMA2_Stream5_IRQHandler GPDMA1_Channel13_IRQHandler
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#define DMA2_Stream6_IRQHandler GPDMA1_Channel14_IRQHandler
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#define DMA2_Stream7_IRQHandler GPDMA1_Channel15_IRQHandler
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#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_GPDMA1EN
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#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_GPDMA1EN
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#define SPI1_RX_DMA_REQUEST GPDMA1_REQUEST_SPI1_RX
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#define SPI1_TX_DMA_REQUEST GPDMA1_REQUEST_SPI1_TX
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#define SPI2_RX_DMA_REQUEST GPDMA1_REQUEST_SPI2_RX
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#define SPI2_TX_DMA_REQUEST GPDMA1_REQUEST_SPI2_TX
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#define SPI3_RX_DMA_REQUEST GPDMA1_REQUEST_SPI3_RX
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#define SPI3_TX_DMA_REQUEST GPDMA1_REQUEST_SPI3_TX
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#define SPI4_RX_DMA_REQUEST GPDMA1_REQUEST_SPI4_RX
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#define SPI4_TX_DMA_REQUEST GPDMA1_REQUEST_SPI4_TX
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#define SPI5_RX_DMA_REQUEST GPDMA1_REQUEST_SPI5_RX
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#define SPI5_TX_DMA_REQUEST GPDMA1_REQUEST_SPI5_TX
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#define SPI6_RX_DMA_REQUEST GPDMA1_REQUEST_SPI6_RX
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#define SPI6_TX_DMA_REQUEST GPDMA1_REQUEST_SPI6_TX
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#define DMA_REQUEST_USART2_RX GPDMA1_REQUEST_USART2_RX
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#define DMA_REQUEST_USART2_TX GPDMA1_REQUEST_USART2_TX
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/* DMA1 stream0 */
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#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
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#define UART2_DMA_RX_IRQHandler DMA1_Stream0_IRQHandler
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#define UART2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
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#define UART2_RX_DMA_INSTANCE DMA1_Stream0
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#define UART2_RX_DMA_REQUEST DMA_REQUEST_USART2_RX
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#define UART2_RX_DMA_IRQ DMA1_Stream0_IRQn
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#endif
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/* DMA1 stream1 */
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#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE)
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#define UART2_DMA_TX_IRQHandler DMA1_Stream1_IRQHandler
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#define UART2_TX_DMA_RCC RCC_AHB1ENR_DMA1EN
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#define UART2_TX_DMA_INSTANCE DMA1_Stream1
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#define UART2_TX_DMA_REQUEST DMA_REQUEST_USART2_TX
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#define UART2_TX_DMA_IRQ DMA1_Stream1_IRQn
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#endif
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/* DMA1 stream2 */
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#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
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#define SPI3_DMA_RX_IRQHandler DMA1_Stream2_IRQHandler
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#define SPI3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
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#define SPI3_RX_DMA_INSTANCE DMA1_Stream2
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#define SPI3_RX_DMA_IRQ DMA1_Stream2_IRQn
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#endif
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/* DMA1 stream3 */
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#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
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#define SPI2_DMA_RX_IRQHandler DMA1_Stream3_IRQHandler
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#define SPI2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
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#define SPI2_RX_DMA_INSTANCE DMA1_Stream3
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#define SPI2_RX_DMA_IRQ DMA1_Stream3_IRQn
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#endif
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/* DMA1 stream4 */
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#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
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#define SPI2_DMA_TX_IRQHandler DMA1_Stream4_IRQHandler
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#define SPI2_TX_DMA_RCC RCC_AHB1ENR_DMA1EN
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#define SPI2_TX_DMA_INSTANCE DMA1_Stream4
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#define SPI2_TX_DMA_IRQ DMA1_Stream4_IRQn
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#endif
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/* DMA1 stream5 */
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#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
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#define SPI3_DMA_TX_IRQHandler DMA1_Stream5_IRQHandler
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#define SPI3_TX_DMA_RCC RCC_AHB1ENR_DMA1EN
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#define SPI3_TX_DMA_INSTANCE DMA1_Stream5
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#define SPI3_TX_DMA_IRQ DMA1_Stream5_IRQn
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#endif
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/* DMA1 stream6 */
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/* DMA1 stream7 */
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#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
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#define SPI3_DMA_TX_IRQHandler DMA1_Stream7_IRQHandler
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#define SPI3_TX_DMA_RCC RCC_AHB1ENR_DMA1EN
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#define SPI3_TX_DMA_INSTANCE DMA1_Stream7
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#define SPI3_TX_DMA_IRQ DMA1_Stream7_IRQn
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#endif
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/* DMA1 stream6/7 are available for SPI6 when SPI3 TX uses stream5. */
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#if defined(BSP_SPI6_RX_USING_DMA) && !defined(SPI6_RX_DMA_INSTANCE)
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#define SPI6_DMA_RX_IRQHandler DMA1_Stream6_IRQHandler
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#define SPI6_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
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#define SPI6_RX_DMA_INSTANCE DMA1_Stream6
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#define SPI6_RX_DMA_IRQ DMA1_Stream6_IRQn
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#endif
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#if defined(BSP_SPI6_TX_USING_DMA) && !defined(SPI6_TX_DMA_INSTANCE)
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#define SPI6_DMA_TX_IRQHandler DMA1_Stream7_IRQHandler
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#define SPI6_TX_DMA_RCC RCC_AHB1ENR_DMA1EN
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#define SPI6_TX_DMA_INSTANCE DMA1_Stream7
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#define SPI6_TX_DMA_IRQ DMA1_Stream7_IRQn
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#endif
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/* DMA2 stream0 */
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#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
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#define SPI1_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler
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#define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
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#define SPI1_RX_DMA_INSTANCE DMA2_Stream0
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#define SPI1_RX_DMA_IRQ DMA2_Stream0_IRQn
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#endif
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/* DMA2 stream1 */
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#if defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE)
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#define SPI4_DMA_TX_IRQHandler DMA2_Stream1_IRQHandler
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#define SPI4_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
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#define SPI4_TX_DMA_INSTANCE DMA2_Stream1
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#define SPI4_TX_DMA_IRQ DMA2_Stream1_IRQn
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#endif
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/* DMA2 stream2 */
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#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
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#define SPI1_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler
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#define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
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#define SPI1_RX_DMA_INSTANCE DMA2_Stream2
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#define SPI1_RX_DMA_IRQ DMA2_Stream2_IRQn
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#endif
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/* DMA2 stream3 */
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#if defined(BSP_SPI5_RX_USING_DMA) && !defined(SPI5_RX_DMA_INSTANCE)
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#define SPI5_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler
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#define SPI5_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
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#define SPI5_RX_DMA_INSTANCE DMA2_Stream3
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#define SPI5_RX_DMA_IRQ DMA2_Stream3_IRQn
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#endif
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/* DMA2 stream4 */
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#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE)
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#define SPI5_DMA_TX_IRQHandler DMA2_Stream4_IRQHandler
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#define SPI5_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
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#define SPI5_TX_DMA_INSTANCE DMA2_Stream4
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#define SPI5_TX_DMA_IRQ DMA2_Stream4_IRQn
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#endif
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/* DMA2 stream5 */
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#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
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#define SPI1_DMA_TX_IRQHandler DMA2_Stream5_IRQHandler
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#define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
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#define SPI1_TX_DMA_INSTANCE DMA2_Stream5
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#define SPI1_TX_DMA_IRQ DMA2_Stream5_IRQn
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#endif
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/* DMA2 stream6 */
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#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE)
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#define SPI5_DMA_TX_IRQHandler DMA2_Stream6_IRQHandler
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#define SPI5_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
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#define SPI5_TX_DMA_INSTANCE DMA2_Stream6
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#define SPI5_TX_DMA_IRQ DMA2_Stream6_IRQn
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#endif
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/* DMA2 stream7 */
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#if defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE)
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#define QSPI_DMA_IRQHandler DMA2_Stream7_IRQHandler
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#define QSPI_DMA_RCC RCC_AHB1ENR_DMA2EN
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#define QSPI_DMA_INSTANCE DMA2_Stream7
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#define QSPI_DMA_IRQ DMA2_Stream7_IRQn
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* __DMA_CONFIG_H__ */

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