|
4 | 4 |
|
5 | 5 | from __future__ import annotations |
6 | 6 |
|
| 7 | +import itertools |
7 | 8 | from dataclasses import dataclass |
8 | 9 | from typing import Optional, Any, TYPE_CHECKING |
9 | 10 |
|
|
22 | 23 | from cuda.tile._memory_model import MemoryScope |
23 | 24 | from cuda.tile._ir.ir import MemoryEffect, add_operation_variadic |
24 | 25 | from cuda.tile._ir.type import TensorLikeTy |
| 26 | +from cuda.lang import _datatype as datatype |
25 | 27 | from cuda.lang._enums import VectorReduction |
26 | 28 | from .ir import Operation, Var, attribute, operand |
27 | 29 | from .type import Type, VectorTy, ScalarTy, PointerTy |
@@ -83,8 +85,7 @@ def generate_llvm(self, ctx): |
83 | 85 | elif len(self.result_vars) == 1: |
84 | 86 | return (result,) |
85 | 87 | else: |
86 | | - return tuple(ctx.builder.extract_value(ctx.typeof(r), result, i) |
87 | | - for i, r in enumerate(self.result_vars)) |
| 88 | + return ctx.unpack_struct(result) |
88 | 89 |
|
89 | 90 |
|
90 | 91 | def call_intrinsic(stub, *args: Var): |
@@ -200,6 +201,71 @@ class InlinePTX(Operation, opcode="inline_ptx", memory_effect=MemoryEffect.STORE |
200 | 201 | text: tuple[InlineAsmPiece, ...] = attribute() |
201 | 202 | inputs: tuple[Var, ...] = operand() |
202 | 203 |
|
| 204 | + @override |
| 205 | + def generate_llvm(self, ctx): |
| 206 | + num_outputs = len(self.result_vars) |
| 207 | + llvm_types = [] |
| 208 | + constraints = [] |
| 209 | + for i, var in enumerate(itertools.chain(self.result_vars, self.inputs)): |
| 210 | + ty = var.get_type() |
| 211 | + assert ty.tensor_shape() == () |
| 212 | + dtype = ty.tensor_dtype() |
| 213 | + code = _dtype_to_inline_ptx_constraint(dtype) |
| 214 | + prefix = "=" if i < num_outputs else "" |
| 215 | + constraints.append(prefix + code) |
| 216 | + llvm_types.append(ctx.typeof(var)) |
| 217 | + |
| 218 | + pieces = [] |
| 219 | + for p in self.text: |
| 220 | + if isinstance(p, str): |
| 221 | + pieces.append(p) |
| 222 | + else: |
| 223 | + if isinstance(p, InlineAsmInput): |
| 224 | + linear_index = num_outputs + p.index |
| 225 | + else: |
| 226 | + assert isinstance(p, InlineAsmOutput) |
| 227 | + linear_index = p.index |
| 228 | + pieces.append(f"${linear_index}") |
| 229 | + |
| 230 | + tt = ctx.builder.type_table |
| 231 | + if num_outputs == 0: |
| 232 | + ret_ty = tt.VOID |
| 233 | + elif num_outputs == 1: |
| 234 | + ret_ty = llvm_types[0] |
| 235 | + else: |
| 236 | + ret_ty = tt.struct_anonymous(llvm_types[:num_outputs]) |
| 237 | + |
| 238 | + func_ty = tt.function(ret_ty, llvm_types[num_outputs:]) |
| 239 | + |
| 240 | + asm = ctx.builder.constants.inline_asm(func_ty, "".join(pieces), ",".join(constraints), |
| 241 | + side_effects=True) |
| 242 | + r = ctx.builder.call(func_ty, asm, [ctx.value(x) for x in self.inputs]) |
| 243 | + |
| 244 | + if num_outputs == 0: |
| 245 | + return () |
| 246 | + elif num_outputs == 1: |
| 247 | + return (r,) |
| 248 | + else: |
| 249 | + return ctx.unpack_struct(r) |
| 250 | + |
| 251 | + |
| 252 | +def _dtype_to_inline_ptx_constraint(dtype: datatype.DType) -> str: |
| 253 | + if dtype == datatype.float32: |
| 254 | + return "f" |
| 255 | + elif dtype == datatype.float64: |
| 256 | + return "d" |
| 257 | + elif dtype == datatype.bool_: |
| 258 | + return "b" |
| 259 | + elif dtype.bitwidth == 16: |
| 260 | + return "h" |
| 261 | + elif dtype.bitwidth == 32: |
| 262 | + return "r" |
| 263 | + elif dtype.bitwidth == 64: |
| 264 | + return "l" |
| 265 | + elif dtype.bitwidth == 128: |
| 266 | + return "q" |
| 267 | + raise NotImplementedError(f"Can't map dtype {dtype} to InlineAsm constraint") |
| 268 | + |
203 | 269 |
|
204 | 270 | @dataclass(eq=False) |
205 | 271 | class Fence(Operation, opcode="fence", memory_effect=MemoryEffect.STORE): |
|
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